UHD software will automatically select the USRP-Embedded FPGA image from the installed images package. The FPGA image selection can be overridden with the
fpga device address parameter.
Example device address string representations to specify non-standard FPGA image:
The master clock rate of the USRP-Embedded feeds both the FPGA DSP and the codec chip. Hundreds of rates between 32 MHz and 64 MHz are available. A few notable rates are:
To use the 61.44 MHz clock rate with the USRP-Embedded, two jumpers must be moved on the device.
J15 is a three pin header; move the jumper to (pin1, pin2).
Note:** See instructions below to communicate the desired clock rate to UHD software.
To use other clock rates, the jumpers will need to be in the default position.
To communicate the desired clock rate into UHD software, specify the a special device address argument, where the key is
master_clock_rate and the value is a rate in Hz. Example:
The E1xx has a 10MHz TCXO which can be used to discipline the flexible clocking by selecting
REF_INT for the uhd::clock_config_t.
Alternately, an external 10MHz reference clock can be supplied by soldering a connector.
An external PPS signal for timestamp synchronization can be supplied by soldering a connector.
Test the PPS input with the following app (
<args> are device address arguments, optional if only one USRP device is on your machine):
cd <install-path>/lib/uhd/examples ./test_pps_input --args=<args>
Please see the Internal GPSDO (USRP-N2x0/E1X0 Models) for information on configuring and using the internal GPSDO.
UHD software will always try to detect an installed GPSDO at runtime. It is not necessary to burn a special EEPROM value for GPSDO detection.
The LEDs on the front panel can be useful in debugging hardware and software issues. The LEDs reveal the following about the state of the device:
The following sensors are available; they can be queried through the API.