#################################################################################### This is a simple documentation file to keep track of the images in this folder Template: ------------------------------------------------------------------------------------ Git hash: <7-chars hash> Target: Source branch: Date: Description: ------------------------------------------------------------------------------------ File usage instructions: - zr_top_cpld.pof -> JTAG programmer (external programmer) - zr_top_cpld_isp_off.svf -> JTAG-engine (legacy mode) - zr_top_cpld.rpd -> reconfig engine #################################################################################### ------------------------------------------------------------------------------------ Git hash: 9ec8d23 Source branch: titanium-master Date: 09/18/2020 Description: Modify timing for GPIO interface compatible with FPGA 4.2 CPLD Revision = 0x20091513 https://ni.visualstudio.com/DevCentral/_build/results?buildId=493229&view=results ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ Git hash: 0785a45 Source branch: titanium-master Date: 09/10/2020 Description: Accomodates for timing changes made to meet timing for GPIO on both ZBX revisions. CPLD revision: 0x20090123 https://ni.visualstudio.com/DevCentral/_build/results?buildId=482603 ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ Git hash: 6b8addb Source branch: titanium-master Date: 08/21/2020 Description: Compared to 44de8d3, this bitstream includes: - enable GPIO interface to reach basic registers of ZBX regmap CPLD revision: 0x20081908 https://ni.visualstudio.com/DevCentral/_build/results?buildId=466349 ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ Git hash: 44de8d3 Source branch: titanium-master Date: 08/04/2020 Description: Compared to d0e1ced, this bitstream includes: - refactor ZBX regmap and add ATR support CPLD revision: 0x20080410 https://ni.visualstudio.com/DevCentral/_build/results?buildId=447357&view=results ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ Git hash: d0e1ced Source branch: titanium-master Date: 07/22/2020 Description: Compared to edd7860, this bitstream includes: - add input stage on DB GPIO interface to relax timing - removing power detection support from rev B - change zbx cpld internal flash config to enable memory init CPLD revision: 0x20071508 https://ni.visualstudio.com/DevCentral/_build/results?buildId=436055&view=results ------------------------------------------------------------------------------------ #################################################################################### Archive #################################################################################### ------------------------------------------------------------------------------------ Git hash: edd7860 Source branch: titanium-master Date: 06/15/2020 Description: This bitstream is the first binary published to orbitty after the refactoring that Javier performed on the ZR CPLD. This includes various reviews, improvements, etc. Including the addition of the ctrlport bytestream interface to the FPGA's GPIOs. https://ni.visualstudio.com/DevCentral/_build/results?buildId=403129&view=results Important! This binary includes the reconfiguration engine to program the CPLD's flash for future updates. This binary still needs to be flashed via JTAG. ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ Git hash: 20191107 (not hash) Source branch: cherwa's local repo Date: 11/07/2019 Description: This bitstream is virtually identical to the one used for the Q3 demo, with the addition of the new SPI format for shorter transactions that is meant for lowering communication time. ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ Git hash: 20191007 (not hash) Source branch: cherwa's local repo Date: 10/07/2019 Description: Q3 demo bitstream. This bitstream fixes the DSA logic in the CPLD. ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ Git hash: 20190927 (not hash) Source branch: cherwa's local repo Date: 09/27/2019 Description: First CPLD image deployed in various systems. This bitstream has an error in the DSA's logic. ------------------------------------------------------------------------------------