X420_FPGA 🔗
This documentation provide a full register map from the X420 FPGA design and the associated CPLDs.The top is defined in HDL source file x420_rfdc_regs.v, x4xx.sv
P1 Content 🔗
Register map for 'X420_FPGA' core team members
This content is intended solely for use by core team members of the 'X420_FPGA' project. Do not distribute or otherwise forward this content. If you believe you have acquired access to this content in error, delete it immediately and notify the sender that you are not intended to have access to this content."All content provided is NI Confidential and Copyright 2026 National Instruments Corporation. For information on NI trademark guidelines, please see http://www.ni.com/legal/trademarks/. For the NI Patent Notice, please see http://www.ni.com/legal/patents/."
ports
Port ARM_M_AXI_HPM0 (input)
Target Regmap = AXI_HPM0_REGMAP
This port is defined in HDL source file x420_rfdc_regs.v.
Port ARM_S_AXI_HPC0 (output)
Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW
This port is defined in HDL source file x420_rfdc_regs.v.
Port ARM_S_AXI_HPC1 (output)
Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW
This port is defined in HDL source file x420_rfdc_regs.v.
Port ARM_SPI1_CS3 (input)
Target Regmap = MB_CPLD_PS_REGMAP
The request format on SPI is defined as.
Write request:
- 1'b1 = write
- 15 bit address
- 32 bit data (MOSI)
- 8 bit processing gap
- 5 bit padding
- 1 bit ack
- 2 bit status
- 1'b0 = read
- 15 bit address
- 8 bit processing gap
- 32 bit data (MISO)
- 5 bit padding
- 1 bit ack
- 2 bit status
This port is defined in HDL source file x420_rfdc_regs.v.
Port RFNoC Radio 0 (input)
Target Regmap = RFNOC_RADIO_REGMAP
This port is defined in HDL source file x420_rfdc_regs.v.
Port RFNoC Radio 1 (input)
Target Regmap = RFNOC_RADIO_REGMAP
This port is defined in HDL source file x420_rfdc_regs.v.
AXI_HPM0_REGMAP 🔗
This is the map for the register space that the Processing System's M_AXI_HPM0_FPD port (AXI4 master interface) has access to. This port has a 40-bit address bus.
COMMON 🔗
Offset 0x80000000: RPU Window (R|W) 🔗
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This window is defined in HDL source file common_regs.v.
Space reserved for RPU access
Offset 0x100003F000: RESERVED Window (R|W) 🔗
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This window is defined in HDL source file common_regs.v.
Register space reserved for future use.
Offset 0x1000080000: MPM_ENDPOINT Window (R|W) 🔗
Target regmap = PL_CPLD_REGMAP
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This window is defined in HDL source file common_regs.v.
MPM endpoint fro MB/DB communication.
Offset 0x10000A0000: CORE_REGS Window (R|W) 🔗
Target regmap = CORE_REGS_REGMAP
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This window is defined in HDL source file common_regs.v.
Register space reserved for mboard-regs (Core).
Offset 0x10000A4000: INT_ETH_DMA Window (R|W) 🔗
Target regmap = ETH_DMA_CTRL_REGMAP
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This window is defined in HDL source file common_regs.v.
AXI DMA engine for internal Ethernet interface.
Offset 0x10000AA000: INT_ETH_REGS Window (R|W) 🔗
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This window is defined in HDL source file common_regs.v.
Misc. registers for internal Ethernet.
Offset 0x1000100000: RFDC Window (R|W) 🔗
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This window is defined in HDL source file common_regs.v.
Register space occupied by the Xilinx RFDC IP block.
Offset 0x1000140000: RFDC_REGS Window (R|W) 🔗
Target regmap = RFDC_REGS_REGMAP
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This window is defined in HDL source file common_regs.v.
Register space for RFDC control/status registers.
UHD_ONLY 🔗
- 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
- 0_1 indicates QSFP0 - Lane1
- 0_2 indicates QSFP0 - Lane2
- 0_3 indicates QSFP0 - Lane3
- 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
- 1_1 indicates QSFP1 - Lane1
- 1_2 indicates QSFP1 - Lane2
- 1_3 indicates QSFP1 - Lane3
Offset 0x1200000000: QSFP_0_0 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x1200010000: QSFP_0_1 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x1200020000: QSFP_0_2 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x1200030000: QSFP_0_3 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x1200040000: QSFP_1_0 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x1200050000: QSFP_1_1 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x1200060000: QSFP_1_2 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x1200070000: QSFP_1_3 Window (R|W) 🔗
Target regmap = QSFP_REGMAP
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This window is defined in HDL source file uhd_regs.v.
MB_CPLD_PS_REGMAP 🔗
This register map is available using the PS CPLD SPI interface.
MB_CPLD_PS_WINDOWS 🔗
Offset 0x0000: PS_REGISTERS Window (R|W) 🔗
Target regmap = PS_CPLD_BASE_REGMAP
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This window is defined in HDL source file mb_cpld.v.
Offset 0x0040: RECONFIG Window (R|W) 🔗
Target regmap = RECONFIG_REGMAP
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This window is defined in HDL source file mb_cpld.v.
Offset 0x0060: POWER_REGISTERS Window (R|W) 🔗
Target regmap = PS_POWER_REGMAP
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This window is defined in HDL source file mb_cpld.v.
PS_SPI_ENDPOINTS 🔗
SPI_ENDPOINT Enumeration 🔗
| Value | Name |
| 0 |
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| 1 |
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| 2 |
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This enumerated type is defined in HDL source file mb_cpld.v.
PL_DMA_MASTER_REGMAP 🔗
This is a regmap to document the different ports that have access to the PS system memory. Each port may have different restrictions on system memory. See the corresponding window for detailsHPC0_DMA 🔗
Offset 0x0000: AXI_HPC0_WINDOW Window (R|W) 🔗
Target port = X420_FPGA|ARM_S_AXI_HPC0
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This window is defined in HDL source file common_regs.v.
| Offset | Size | Description |
|---|---|---|
| 0x000800000000 | 0x000800000000 | DDR_HIGH |
| 0x00000000 | 0x80000000 | DDR_LOW |
| 0xFF000000 | 0x01000000 | LPS_OCM |
| 0xC0000000 | 0x20000000 | QSPI |
HPC1_DMA 🔗
Offset 0x0000: AXI_HPC1_WINDOW Window (R|W) 🔗
Target port = X420_FPGA|ARM_S_AXI_HPC1
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This window is defined in HDL source file common_regs.v.
| Offset | Size | Description |
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| 0x000800000000 | 0x000800000000 | DDR_HIGH |
| 0x00000000 | 0x80000000 | DDR_LOW |
| 0xC0000000 | 0x20000000 | QSPI |
RFNOC_RADIO_REGMAP 🔗
RFNOC_RADIO_WINDOWS 🔗
RFNoC control requests are distributed across the following windows. The shared and periphial windows are capable of handling timed requests.Offset 0x0000: SHARED_WINDOW Window (R|W) 🔗
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This window is defined in HDL source file rfnoc_block_radio.v.
Offset 0x1000: RFDC_TIMING_WINDOW Window (R|W) 🔗
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This window is defined in HDL source file rfnoc_block_radio.v.
Offset 0x80000: PERIPH_WINDOW Window (R|W) 🔗
Target regmap = RADIO_CTRLPORT_REGMAP
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This window is defined in HDL source file rfnoc_block_radio.v.
RF_CORE_REGMAP 🔗
IQ_IMPAIRMENT_WINDOWS 🔗
Offset 0x0000: TX_IQ_IMPAIRMENTS Window (R|W) 🔗
Target regmap = IQ_IMPAIRMENT_REGMAP
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This window is defined in HDL source file rf_core_1000m.sv.
Offset 0x0020: RX_IQ_IMPAIRMENTS Window (R|W) 🔗
Target regmap = IQ_IMPAIRMENT_REGMAP
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This window is defined in HDL source file rf_core_1000m.sv.
Offset 0x0040: TX_DC_OFFSET Window (R|W) 🔗
Target regmap = DC_OFFSET_REGMAP
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This window is defined in HDL source file rf_core_1000m.sv.
Offset 0x0050: RX_DC_OFFSET Window (R|W) 🔗
Target regmap = DC_OFFSET_REGMAP
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This window is defined in HDL source file rf_core_1000m.sv.
ADMV_CONTROL_REGMAP 🔗
ADMV_CONTROL_REGISTERS 🔗
Controls the SPI transaction to the ADMV chips.Offset 0x0000: ADMV_SPI_INFO Register (R) 🔗
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Initial Value = 0x00000C08
This register is defined in HDL source file admv_control.sv.
Offset 0x0004: ADMV_SPI_SETUP Register (W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file admv_control.sv.
Offset 0x0008: ADMV_SPI_STATUS Register (R) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file admv_control.sv.
| Bits | Name |
| 31 |
ADMV_SPI_READY (initialvalue=0) If this bit returns '1' then the ADMV chip is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. Poll this bit before starting an SPI transaction. |
| 30 |
ADMV_SPI_DATA_VALID (initialvalue=0) Returns '1' when a read SPI transaction is complete.
If it returns '0' then it is busy with a previous SPI read. |
| 29..24 |
Reserved |
| 23..20 |
Reserved |
| 19..8 |
ADMV_SPI_RD_ADDR (initialvalue=0) Returns the address (write or read) of the last SPI transaction. This bit field will retain it's old value until a new SPI transaction has finished. The value in here will be a copy of ADMV_SPI_WT_ADDR. |
| 7..0 |
ADMV_SPI_RD_DATA (initialvalue=0) Returns the data of the last SPI read. This bit field will retain it's old value until a new SPI read transaction has finished i.e. ADMV_SPI_DATA_VALID returns '1'. |
Offset 0x000C: ADMV_CONTROL Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file admv_control.sv.
ATR_CONTROLLER_REGMAP 🔗
ATR_REGISTERS 🔗
This regmap contains settings for the active configuration of the RF port. There is one configuration set for RF switches, LEDs, and attenuators (DSA).ATR_OPTIONS Enumeration 🔗
Contains the options available for the RF port. The chosen setting affects how the active configuration of up to 8 bits is derived.| Value | Name |
| 0 |
Uses the respective value of SW_CONFIG_REG as configuration. |
| 1 |
This option assumes the FPGA state to be assigned with:
Bit 0 = RX running, Bit 1 = TX running. |
This enumerated type is defined in HDL source file atr_controller.sv.
Offset 0x0000: CURRENT_CONFIG_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file atr_controller.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..0 |
Current active configuration for switches, LEDs and DSAs of the RF port. |
Offset 0x0004: OPTION_REG Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file atr_controller.sv.
| Bits | Name | ||||||
| 31..24 |
Reserved |
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| 23..16 |
Reserved |
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| 15..8 |
Reserved |
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| 7..1 |
Reserved |
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| 0 |
RF_OPTION (initialvalue=SW_DEFINED) Option used for switches, LEDs and DSAs of the RF port. The values for this bitfield are in the ATR_OPTIONS table. (show herehide)
This enumerated type is defined in HDL source file atr_controller.sv. |
Offset 0x0008: SW_CONFIG_REG Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file atr_controller.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..0 |
SW defined configuration for switches, LEDs and DSAs of the RF port. |
BASIC_REGS_REGMAP 🔗
BASIC_REGS_REGISTERS 🔗
This regmap contains the revision registers, signature register, a scratch register, and a slave control reg.BASIC_REGISTERS_VALUES Enumeration 🔗
This enum is used to create the constants held in the basic registers in both verilog and vhdl.| Value | Name | |
| Dec | Hex | |
| 16392 | 0x00004008 | |
| 621815574 | 0x25102716 | |
| 621938960 | 0x25120910 | |
This enumerated type is defined in HDL source file basic_regs.sv.
Offset 0x0000: SLAVE_SIGNATURE Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file basic_regs.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
Board ID corresponds to the last 16 digits of the daughterboard part number. |
Offset 0x0004: SLAVE_REVISION Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file basic_regs.sv.
| Bits | Name |
| 31..0 |
Returns the revision in YYMMDDHH format |
Offset 0x0008: SLAVE_OLDEST_REVISION Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file basic_regs.sv.
| Bits | Name |
| 31..0 |
Returns the oldest compatible revision in YYMMDDHH format |
Offset 0x000C: SLAVE_SCRATCH Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file basic_regs.sv.
| Bits | Name |
| 31..0 |
Returns the value written here previously. |
Offset 0x0010: GIT_HASH_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file basic_regs.sv.
Value equals 0xDEADBEEF if the git hash was not used during synthesis.
| Bits | Name |
| 31..28 |
0x0 in case the git status was clean |
| 27..0 |
7 hex digit hash code of the commit |
CMAC_REGMAP 🔗
XILINX_CMAC_REGISTERS 🔗
100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.
- http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
CORE_REGS_REGMAP 🔗
This is the map for the registers that the CORE_REGS window has access to from the ARM_AXI_HPM0_FPD port. The registers contained here conform the mboard-regs node that MPM uses to manage general FPGA control/status calls, such as versioning, timekeeper, GPIO, etc. The following diagram shows how the communication bus interacts with the modules in CORE_REGS.
CORE_REGS 🔗
Offset 0x0000: GLOBAL_REGS Window (R|W) 🔗
Target regmap = GLOBAL_REGS_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0x0C00: VERSIONING_REGS Window (R|W) 🔗
Target regmap = VERSIONING_REGS_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0x1000: TIMEKEEPER_A Window (R|W) 🔗
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0x1100: TIMEKEEPER_B Window (R|W) 🔗
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0x2000: DIO Window (R|W) 🔗
Target regmap = DIO_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
CPLD_INTERFACE_REGMAP 🔗
CPLD_INTERFACE_REGS 🔗
Basic registers containing version and capabilities information.Offset 0x0000: SIGNATURE_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file cpld_interface_regs.v.
| Bits | Name |
| 31..0 |
fixed value 0xCB1D1FAC |
Offset 0x000C: SCRATCH_REGISTER Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file cpld_interface_regs.v.
CPLD_SPI_CONTROL_REGS 🔗
Registers to control the SPI clock frequency of the CPLD interfaces. The resulting clock frequency is calculated by .Note that the PLL Reference Clock (PRC) is depending on the RF clocks.
Offset 0x0020: MOTHERBOARD_CPLD_DIVIDER Register (R|W) 🔗
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Initial Value = 0x00000002
This register is defined in HDL source file cpld_interface_regs.v.
Minimum required value is 2.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
Divider value |
Offset 0x0024: DAUGHTERBOARD_CPLD_DIVIDER Register (R|W) 🔗
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Initial Value = 0x00000005
This register is defined in HDL source file cpld_interface_regs.v.
Minimum required value is 5.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
Divider value |
IPASS_REGS 🔗
Offset 0x0010: IPASS_CONTROL Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file cpld_interface_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
If 1 enables the forwarding of iPass cable present signal to MB CPLD using ctrlport requests. On change from 0 to 1 the current status is transferred to the MB CPLD via SPI ctrlport request initially. |
DB_CONTROL_REGMAP 🔗
DB_CONTROL_WINDOWS 🔗
Offset 0x0000: TX_LO_SYNTH_CONTROL Window (R|W) 🔗
Target regmap = LO_SYNTH_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0010: RX_LO_SYNTH_CONTROL Window (R|W) 🔗
Target regmap = LO_SYNTH_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0020: TX_ADMV_CONTROL Window (R|W) 🔗
Target regmap = ADMV_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0030: RX_ADMV_CONTROL Window (R|W) 🔗
Target regmap = ADMV_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0040: IQ_DEMOD_CONTROL Window (R|W) 🔗
Target regmap = IQ_DEMOD_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0050: TX_LO_PD_ADC_CONTROL Window (R|W) 🔗
Target regmap = LO_PD_ADC_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0060: RX_LO_PD_ADC_CONTROL Window (R|W) 🔗
Target regmap = LO_PD_ADC_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0070: RX_RF_PD Window (R|W) 🔗
Target regmap = RX_RF_PD_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0080: DB_CONTROL_GPIO_DUMMIES Window (R|W) 🔗
Target regmap = GPIO_DUMMY_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x00A0: ATR_CONTROLLER Window (R|W) 🔗
Target regmap = ATR_CONTROLLER_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x1000: RF_SWITCHES Window (R|W) 🔗
Target regmap = RF_SWITCHES_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x2000: DSA_CONTROL Window (R|W) 🔗
Target regmap = DSA_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x3000: LED_CONTROL_REGMAP Window (R|W) 🔗
Target regmap = LED_CONTROL_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
DB_WINDOW_REGMAP 🔗
This is a dummy regmap to have a common name for DB specific window to refer to.DB_WINDOW 🔗
Offset 0x0000: DB_GPIO_WINDOW Window (R|W) 🔗
Target regmap = GPIO_REGMAP
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||||||||||
|
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This window is defined in HDL source file db_gpio_interface.sv.
Offset 0x7000: FPGA_GPIO_WINDOW Window (R|W) 🔗
Target regmap = FPGA_GPIO_REGMAP
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||||||||||
|
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This window is defined in HDL source file db_gpio_interface.sv.
DC_OFFSET_REGMAP 🔗
DC_OFFSET_REGISTERS 🔗
This register map contains the registers used to configure the DC offset correction block.MODE_TYPE Enumeration 🔗
| Value | Name |
| 0 |
Bypass mode. The input samples are passed to the output without any processing. |
| 1 |
Correction mode. The DC offset of OFFSET_VALUE_REG is applied to the input samples. |
This enumerated type is defined in HDL source file dc_offset.sv.
Offset 0x0000: CONTROL_REG Register (R|W) 🔗
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|||||||||||
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|||||||||||||||
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||||||||||||||
|
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Initial Value not specified
This register is defined in HDL source file dc_offset.sv.
| Bits | Name | ||||||
| 31..24 |
Reserved |
||||||
| 23..16 |
Reserved |
||||||
| 15..8 |
Reserved |
||||||
| 7..1 |
Reserved |
||||||
| 0 |
The values for this bitfield are in the MODE_TYPE table. (show herehide)
This enumerated type is defined in HDL source file dc_offset.sv. |
Offset 0x0004: OFFSET_VALUE_REG Register (R|W) 🔗
|
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|||||||||||
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|||||||||||||||
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|
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Initial Value not specified
This register is defined in HDL source file dc_offset.sv.
| Bits | Name |
| 31..16 | |
| 15..0 |
DIG_IFC_REGMAP 🔗
SPI_OVER_GPIO_REGS 🔗
Offset 0x0000: SPI_SLAVE_CONFIG (3:0) Register Array (R|W) 🔗
|
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|
|||||||||||
|
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Intial Values
| default | => | 0x00000000 |
This register is defined in HDL source file x4xx_gpio_spi.v.
It uses RegType SPI_SETUP which is
defined in HDL source file x4xx_gpio_spi.v.
Set of configuration registers for the supported slaves. Starting from FPGA compat number 10.1, the bit order for "Port A GPIO" and "Port B GPIO" matches the pin order of the "DIO" signals on the frontpanel connectors (which is the same order as the HDMI pin numbering with ground pins and pin 14 (HEC/ARC) left out). Up until FPGA compat number 10.0, software had to apply a mapping on software side to compensate for non-linear mapping in the FPGA.
| Bits | Name |
| 31..28 |
Reserved |
| 27 |
Controls the edge in which the MOSI line is updated. 0 = falling edge of SCLK. 1 = rising edge of SCLK. |
| 26 |
Controls the edge in which the MISO line is latched. 0 = falling edge of SCLK. 1 = rising edge of SCLK. |
| 25..20 |
Indicates the length of SPI transactions to this slave. |
| 19..15 |
Indicates which GPIO line to use for the CS signal. 0-11 : Port A GPIO 16-27: Port B GPIO |
| 14..10 |
Indicates which GPIO line to use for the MISO signal. 0-11 : Port A GPIO 16-27: Port B GPIO |
| 9..5 |
Indicates which GPIO line to use for the MOSI signal. 0-11 : Port A GPIO 16-27: Port B GPIO |
| 4..0 |
Indicates which GPIO line to use for the SCLK signal. 0-11 : Port A GPIO 16-27: Port B GPIO |
Offset 0x0010: SPI_TRANSACTION_CONFIG Register (R|W) 🔗
|
|
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|
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|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_spi.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..18 |
Reserved |
| 17..16 | |
| 15..0 |
Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)] |
Offset 0x0014: SPI_TRANSACTION_GO Register (W) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_spi.v.
| Bits | Name |
| 31..0w |
Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits, it must be aligned to the MSbs in this field. LSbs are ignored in this scenario. |
Offset 0x0018: SPI_STATUS Register (R) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_spi.v.
| Bits | Name |
| 31..25 |
Reserved |
| 24 |
Indicates the SPI engine is ready to start a new SPI transaction. |
| 23..0 |
Records the response of the last completed SPI transaction. |
Offset 0x001C: CONTROLLER_INFO Register (R) 🔗
|
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|
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|
|||||||||||
|
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Initial Value not specified
This register is defined in HDL source file x4xx_gpio_spi.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..4 |
Reserved |
| 3..0 |
Indicates the number SPI slaves configurable by the controller. |
DIO_REGMAP 🔗
DIO_REGS 🔗
Registers to control the GPIO buffer direction on the FPGA connected to the DIO board. Further registers enable different sources to control and read the GPIO lines as master. The following diagram shows how source selection multiplexers are arranged, as well as an indicator for the register that control them.
Make sure the GPIO lines between FPGA and GPIO board are not driven by
two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.
Important note on the bit ordering inside the DIO_PORT_A and DIO_PORT_B bitfields of all DIO-registers:
-
Starting from FPGA compat number 10.1, the bit order matches the pin
order of the "DIO" signals on the frontpanel connectors (which is the
same order as the HDMI pin numbering with ground pins and pin 14
(HEC/ARC) left out):
+----------------------------------------+ | 11 -- 09 08 -- 05 04 -- 01 00 | \ -- 10 -- 07 06 -- 03 02 -- / +--------------------------------------+
- Up until FPGA compat number 10.0, the bit order did not match the actual pin order on the frontpanel connectors. To compensate for this, the software had to apply a mapping table for the values in bitfield DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another mapping table for the values in bitfield DIO_PORT_B (see parameter 'MAPPED_PIN_DIO_B' in x4xx.sv).
Offset 0x0000: DIO_MASTER_REGISTER Register (R|W) 🔗
|
|
|
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|
||||||||||
|
|
|
|
|
||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Sets whether the DIO signal line is driven by this register interface or the user application.
0 = user application is master, 1 = output of SW_DIO_CONTROL is master
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0004: DIO_DIRECTION_REGISTER Register (R|W) 🔗
|
|
|
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|
||||||||||
|
|
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|
||||||||||
|
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Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Set the direction of FPGA buffer connected to DIO ports on the DIO board.
Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0008: DIO_INPUT_REGISTER Register (R) 🔗
|
|
|
|
|
||||||||||
|
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|
||||||||||
|
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Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Status of each bit at the FPGA input.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x000C: DIO_OUTPUT_REGISTER Register (R|W) 🔗
|
|
|
|
|
||||||||||
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|
||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Controls the values on each DIO signal line in case the line master is set to PS in DIO_MASTER_REGISTER.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0010: DIO_SOURCE_REGISTER Register (R|W) 🔗
|
|
|
|
|
||||||||||
|
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|
||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER or the radio blocks. 0 = DIO_MASTER_REGISTER, 1 = Radio block output(DIO_OVERRIDE)
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0014: RADIO_SOURCE_REGISTER Register (R|W) 🔗
|
|
|
|
|
||||||||||
|
|
|
|
|
||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Controls which radio block to use the ATR state from to determine the state of the DIO lines. 0 = Radio#0 1 = Radio#1
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0018: INTERFACE_DIO_SELECT Register (R|W) 🔗
|
|
|
|
|
||||||||||
|
|
|
|
|
||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Controls which of the two available digital interfaces controls the DIO lines. 0 = Digital interface from Radio#0, 1 = Digital Interface from Radio#1.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x001C: DIO_OVERRIDE Register (R|W) 🔗
|
|
|
|
|
||||||||||
|
|
|
|
|
||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Controls whether the radio input to the DIO_SOURCE_REGISTER mux connects to the ATR control or a Digital interface block. The output of the mux controlled by this bit goes to DIO_SOURCE_REGISTER. 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive Digital interface block(Output of INTERFACE_DIO_SELECT).
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0020: SW_DIO_CONTROL Register (R|W) 🔗
|
|
|
|
|
||||||||||
|
|
|
|
|
||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
It uses RegType DIO_CONTROL_REG which is
defined in HDL source file x4xx_dio.v.
Controls which source is forwarded to the DIO_MASTER_REGISTER mux. This configuration is applied independently for each DIO line. 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
DMA_REGMAP 🔗
XILINX_DMA_REGISTERS 🔗
Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
- https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
DSA_CONTROL_REGMAP 🔗
DSA_CONTROL_REGISTERS 🔗
This regmap contains the registers to control the HBX digital step attenuators (DSA).Offset 0x0000: TX_RF_DSA_REG (255:0) Register Array (R|W) 🔗
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|||||||||||||||||||||
|
|
|
|
|
|
|||||||||||||||||
|
|
Intial Values
| default | => | 0x0000005C |
This register is defined in HDL source file dsa_control_regs.sv.
It uses RegType TX_RF_DSA_REG_TYPE which is
defined in HDL source file dsa_control_regs.sv.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..6 |
Reserved |
| 5..1 |
Set values from 0 to 46 dB in 2 dB steps. The initial value will be applied after IO_ENABLE is set. |
| 0 |
Reserved |
Offset 0x0400: RX_RF_DSA_REG (255:0) Register Array (R|W) 🔗
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|||||||||||||||||||||
|
|
|
|
|
|
|||||||||||||||||
|
|
Intial Values
| default | => | 0x001F1F5C |
This register is defined in HDL source file dsa_control_regs.sv.
It uses RegType RX_RF_DSA_REG_TYPE which is
defined in HDL source file dsa_control_regs.sv.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 |
Reserved |
| 23..21 |
Reserved |
| 20..16 |
Set values between 0 and 31 dB in 1 dB steps. |
| 15..13 |
Reserved |
| 12..8 |
Set values between 0 and 31 dB in 1 dB steps. |
| 7..6 |
Reserved |
| 5..1 |
Set values from 0 to 46 dB in 2 dB steps. The initial value will be applied after IO_ENABLE is set. |
| 0 |
Reserved |
Offset 0x0800: TX_LO_DSA_REG (255:0) Register Array (R|W) 🔗
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|||||||||||||||||||||
|
|
|
|
|
|
|||||||||||||||||
|
|
Intial Values
| default | => | 0x0000001F |
This register is defined in HDL source file dsa_control_regs.sv.
It uses RegType TX_LO_DSA_REG_TYPE which is
defined in HDL source file dsa_control_regs.sv.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..5 |
Reserved |
| 4..0 |
Set values between 0 and 31 dB in 1 dB steps. |
Offset 0x0C00: RX_LO_DSA_REG (255:0) Register Array (R|W) 🔗
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|||||||||||||||||||||
|
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|
|
|
|
|||||||||||||||||
|
|
Intial Values
| default | => | 0x0000001F |
This register is defined in HDL source file dsa_control_regs.sv.
It uses RegType RX_LO_DSA_REG_TYPE which is
defined in HDL source file dsa_control_regs.sv.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..5 |
Reserved |
| 4..0 |
Set values between 0 and 31 dB in 1 dB steps. |
ETH_DMA_CTRL_REGMAP 🔗
This is the map that the nixge driver uses in Ethernet DMA to move data between the Processing System's architecture and the fabric. This map is a combination of two main components: a Xilix AXI DMA engine and some registers for MAC/PHY control.ETH_DMA_CTRL 🔗
Offset 0x0000: AXI_DMA_CTRL Window (R|W) 🔗
|
|
|
|
This window is defined in HDL source file common_regs.v.
Offset 0x4000: ETH_IO_CTRL Window (R|W) 🔗
|
|
|
|
This window is defined in HDL source file common_regs.v.
FPGA_GPIO_REGMAP 🔗
Content in the GPIO address space which is implemented in the FPGA.FPGA_GPIO_WINDOW 🔗
Offset 0x0000: SYNC_INJECTION_WINDOW Window (R|W) 🔗
Target regmap = HBX_SYNC_INJECTION_REGMAP
|
|
|
|
|
|
||||||||||||
|
|
This window is defined in HDL source file db_gpio_interface.sv.
GLOBAL_REGS_REGMAP 🔗
GLOBAL_REGS 🔗
Offset 0x0000: COMPAT_NUM_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..16 | |
| 15..0 |
Offset 0x0004: DATESTAMP_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..27 | |
| 26..23 | |
| 22..17 |
This is the year number after 2000 (e.g. 2019 = d19). |
| 16..12 | |
| 11..6 | |
| 5..0 |
Offset 0x0008: GIT_HASH_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x000C: SCRATCH_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0010: DEVICE_ID_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31 |
Set to 1 if PCI-Express core is present in FPGA design. |
| 30..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
Offset 0x0014: RFNOC_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..16 | |
| 15..8 | |
| 7..0 |
Offset 0x0018: CLOCK_CTRL_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..24 |
Number of base reference clock cycles from appearance of the PPS
rising edge to the occurrence of the aligned edge of base reference
clock and PLL reference clock at the sample PLL output. This number
is the sum of the actual value based on PLL_SYNC_DELAY (also
accumulate the fixed amount of clock cycles) and if any the number of
cycles the SPLL requires from issuing of the SYNC signal to the
aligned edge (with LMK04832 = 0). |
| 23..16 |
Due to the HDL implementation the rising edge of the SYNC signal for
the LMK04832 is generated 2 clock cycles after the PPS rising edge.
This delay can be further increased by setting this delay value
(e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles). |
| 15..10 |
Reserved |
| 9r |
Indicates the success of the PLL reset started by PLL_SYNC_TRIGGER. Reset on deassertion of PLL_SYNC_TRIGGER. |
| 8w |
Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge. There is no self reset on this trigger. Keep this trigger asserted until PLL_SYNC_DONE is asserted. |
| 7..6 |
Reserved |
| 5..4 |
TRIGGER_IO_SELECT (initialvalue=TRIG_IO_INPUT) IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore and/or re-sync after enabling this port, since the output-enable is basically asynchronous to the actual TRIG_IO driver. |
| 3r |
RESERVED. This bit is not implemented on X4xx and reads as 0. |
| 2 |
RESERVED. This bit is not implemented on X4xx and reads as 0. |
| 1..0 |
PPS_SELECT (initialvalue=PPS_INT_25MHZ) Select the source of the PPS signal. For the internal generation the value depending on the base reference clock has to be chosen. The external reference is taken from the PPS_IN pin and is independent of the base reference clock. |
Offset 0x001C: PPS_CTRL_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31 |
Enables the PPS signal in radio clock domain. Please make sure that the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and PRC_RC1_DIVIDER are set before enabling this bit. It is recommended to disable the PPS for changes on the other values. Use a wait time of at least 1 second before changing this value to ensure the values are stable for the next PPS edge. |
| 30..26 |
Reserved |
| 25..0 |
The number of PLL reference clock cycles from one aligned edge to the
desired aligned edge to issue the PPS in radio clock domain. This
delay is configurable to any aligned edge within a maximum delay of 1
second (period of PPS). |
Offset 0x0020: CHDR_CLK_RATE_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..0 |
Offset 0x0024: CHDR_CLK_COUNT_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0028: BUILD_SEED_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0030: PPS_CROSSING_REG Register (R|W) 🔗
|
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|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..21 |
Reserved |
| 20..16 |
Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to follow the following formula:
|
| 15..8 |
Reserved |
| 7..5 |
Reserved |
| 4..0 |
Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to follow the following formula:
|
Offset 0x0038: GPS_CTRL_REG Register (R|W) 🔗
|
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|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x003C: GPS_STATUS_REG Register (R) 🔗
|
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|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0040: DBOARD_CTRL_REG Register (R|W) 🔗
|
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|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0044: DBOARD_STATUS_REG Register (R) 🔗
|
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|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0048: NUM_TIMEKEEPERS_REG Register (R) 🔗
|
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|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x004C: SERIAL_NUM_LOW_REG Register (R|W) 🔗
|
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|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0050: SERIAL_NUM_HIGH_REG Register (R|W) 🔗
|
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|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0054: MFG_TEST_CTRL_REG Register (R|W) 🔗
|
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|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1 |
When enabled, routes data_clk to FPGA_REF_CLK output port. When disabled, the FPGA_REF_CLK output is driven to 0. |
| 0 |
When enabled, routes data_clk to GTY_RCV_CLK output port. When disabled, the GTY_RCV_CLK output is driven to 0. |
Offset 0x0058: MFG_TEST_STATUS_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..26 |
Reserved |
| 25..0 |
Report the time between rising edges on the FPGA_REF_CLK input port in 40 MHz Clock ticks. If the count extends to 1.2 seconds without an edge, the value reported is set to zero. |
Offset 0x0060: QSFP_PORT_0_0_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0064: QSFP_PORT_0_1_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0068: QSFP_PORT_0_2_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x006C: QSFP_PORT_0_3_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0070: QSFP_PORT_1_0_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0074: QSFP_PORT_1_1_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0078: QSFP_PORT_1_2_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x007C: QSFP_PORT_1_3_INFO_REG Register (R) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0100: DEVICE_DNA0_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0104: DEVICE_DNA1_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
Offset 0x0108: DEVICE_DNA2_REG Register (R|W) 🔗
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
GPIO_ATR_REGMAP 🔗
GPIO_ATR_REGS 🔗
Describes the behavior of GPIO lines when controlled by the ATR state.Important note on the bit ordering inside the (...)_A and (...)_B bitfields of all ATR-registers:
- Starting from FPGA compat number 10.1, the bit order matches the pin order of the "DIO" signals on the frontpanel connectors (which is the same order as the HDMI pin numbering with ground pins and pin 14 (HEC/ARC) left out).
- Up until FPGA compat number 10.0, the bit order did not match the actual pin order on the frontpanel connectors. To compensate for this, the software had to apply a mapping table for the values in bitfield DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another mapping table for the values in bitfield DIO_PORT_B (see parameter 'MAPPED_PIN_DIO_B' in x4xx.sv).
Offset 0x0000: ATR_STATE (15:0) Register Array (R|W) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Intial Values
| default | => | 0x00000000 |
This register is defined in HDL source file x4xx_gpio_atr.v.
It uses RegType GPIO_ATR_STATE which is
defined in HDL source file x4xx_gpio_atr.v.
Describes GPIO behavior for the different ATR states. When ATR_OPTION is set to use the DB states, TX and RX states for RF0 and RF1 are combined to create a single vector. This creates 16 different combinations, each with its own register. When ATR_OPTION is set to classic ATR, offsets 0x00-0x03 in this register group will be driven in accordance with the state of RF0, and offsets 0x04-0x07 will be driven in accordance with the state of RF1. CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05], TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0040: CLASSIC_ATR_CONFIG Register (R|W) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_atr.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 |
Set which RF channel's state to reflect in the pins of HDMI connector B when ATR_OPTION is set to classic ATR. Controlled in a per-pin basis. 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07) |
| 15..12 |
Reserved |
| 11..0 |
Set which RF channel's state to reflect in the pins for HDMI connector A when ATR_OPTION is set to classic ATR. Controlled in a per-pin basis. 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07) |
Offset 0x0044: ATR_OPTION_REGISTRER Register (R|W) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_atr.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Sets the scheme in which RF states in the radio will control GPIO lines. 0 = DB state is used. RF states are combined and the GPIO state is driven based on all 16 ATR_STATE registers. 1 = Each RF channel has its separate ATR state(Classic ATR). Use register CLASSIC_ATR_CONFIG to indicate the RF channel to which each GPIO line responds to. |
Offset 0x0048: GPIO_DIR Register (R|W) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_atr.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x004C: GPIO_DISABLED Register (R|W) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_atr.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
Offset 0x0050: GPIO_IN Register (R|W) 🔗
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_gpio_atr.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
GPIO_DUMMY_REGMAP 🔗
GPIO_REGS 🔗
This regmap contains registers to assign values to outputs and read inputs.Offset 0x0000: GPIO_OUTPUT_REG (3:0) Register Array (W) 🔗
|
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|||||||||||||||
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|||||||||||||||||||||
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|||||||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file gpio_dummies.sv.
It uses RegType GPIO_OUTPUT_TYPE which is
defined in HDL source file gpio_dummies.sv.
Offset 0x0010: GPIO_INPUT_REG (3:0) Register Array (R) 🔗
|
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|||||||||||||||
|
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|||||||||||||||||||||
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|||||||||||||||||
|
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Initial Value not specified
This register is defined in HDL source file gpio_dummies.sv.
It uses RegType GPIO_INPUT_TYPE which is
defined in HDL source file gpio_dummies.sv.
GPIO_REGMAP 🔗
GPIO_REGMAP_WINDOWS 🔗
Offset 0x0000: BASE_WINDOW_GPIO Window (R|W) 🔗
Target regmap = BASIC_REGS_REGMAP
|
|
|
|
|
|
||||||||||||
|
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x1000: DB_CONTROL_WINDOW_GPIO Window (R|W) 🔗
Target regmap = DB_CONTROL_REGMAP
|
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|
|
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|
||||||||||||
|
|
This window is defined in HDL source file hbx_top_cpld.sv.
HBX_SPI_REGMAP 🔗
SPI_REGMAP_WINDOWS 🔗
Offset 0x0000: BASE_WINDOW_SPI Window (R|W) 🔗
Target regmap = BASIC_REGS_REGMAP
|
|
|
|
|
|
||||||||||||
|
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0020: POWER_REGS Window (R|W) 🔗
Target regmap = POWER_REGS_REGMAP
|
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|
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|
||||||||||||
|
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x0040: RECONFIG_REGS Window (R|W) 🔗
Target regmap = LATTICE_RECONFIG_REGMAP
|
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|
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|
||||||||||||
|
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This window is defined in HDL source file hbx_top_cpld.sv.
Offset 0x1000: DB_CONTROL_WINDOW_SPI Window (R|W) 🔗
Target regmap = DB_CONTROL_REGMAP
|
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|
||||||||||||
|
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This window is defined in HDL source file hbx_top_cpld.sv.
HBX_SYNC_INJECTION_REGMAP 🔗
HBX_SYNC_INJECTION_REGISTERS 🔗
Control of the HBX sync injection clock.Offset 0x0000: CLK_EN_CONTROL Register (R|W) 🔗
|
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|
|||||||||||||
|
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Initial Value = 0x00000000
This register is defined in HDL source file hbx_sync_injection.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Enables the Clock. |
IQ_DEMOD_CONTROL_REGMAP 🔗
IQ_DEMOD_CONTROL_REGISTERS 🔗
Controls the SPI transaction to the RX IQ Demodulator LTC5594.Offset 0x0000: IQ_DEMOD_SPI_INFO Register (R) 🔗
|
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|||||||||||||||
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|||||||||||||||||||||
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|||||||||||||||||
|
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Initial Value = 0x00000708
This register is defined in HDL source file iq_demod_control.sv.
Offset 0x0004: IQ_DEMOD_SPI_SETUP Register (W) 🔗
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|||||||||||||||
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|||||||||||||||||||||
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|||||||||||||||||
|
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Initial Value = 0x00000000
This register is defined in HDL source file iq_demod_control.sv.
Offset 0x0008: IQ_DEMOD_SPI_STATUS Register (R) 🔗
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|||||||||||||||
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|||||||||||||||||||||
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|||||||||||||||||
|
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Initial Value = 0x00000000
This register is defined in HDL source file iq_demod_control.sv.
| Bits | Name |
| 31 |
IQ_DEMOD_SPI_READY (initialvalue=0) If this bit returns '1' then IQ Demodulator is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. Poll this bit before starting an SPI transaction. |
| 30 |
IQ_DEMOD_SPI_DATA_VALID (initialvalue=0) Returns '1' when a read SPI transaction is complete.
If it returns '0' then it is busy with a previous SPI read. |
| 29..24 |
Reserved |
| 23..16 |
Reserved |
| 15 |
Reserved |
| 14..8 |
IQ_DEMOD_SPI_RD_ADDR (initialvalue=0) Returns the address (write or read) of the last SPI transaction. This bit field will retain it's old value until a new SPI transaction has finished. The value in here will be a copy of IQ_DEMOD_SPI_WT_ADDR. |
| 7..0 |
IQ_DEMOD_SPI_RD_DATA (initialvalue=0) Returns the data of the last SPI read. This bit field will retain it's old value until a new SPI read transaction has finished i.e. IQ_DEMOD_SPI_DATA_VALID returns '1'. |
IQ_IMPAIRMENT_REGMAP 🔗
IQ_IMPAIRMENT_REGISTERS 🔗
This register map contains the registers used to configure the IQ impairment correction block. The I output of the block is a delayed version of the I input scaled by the IINLINE_COEFF factor. The delay is determined by the GROUP_DELAY register and the processing delay of the FIR filters. The Q output of the block is a combination of the Q input and the I input. The I input is filtered by the I cross FIR filter and the Q input is filtered by the Q inline FIR filter. The outputs of both filters are added, rounded and clipped to calculate the Q output. The FIR filters boot up with all coefficients set to 0. Ensure to set a non-zero coefficient before running data through the filters.Offset 0x0000: DSP_REG Register (R) 🔗
|
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|||||||||||
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|||||||||||||||
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||||||||||||||
|
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Initial Value not specified
This register is defined in HDL source file impairment_correction.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..0 |
This field contains the number of coefficients used in the FIR filters. |
Offset 0x0004: DELAY_REG Register (R|W) 🔗
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|
|
|||||||||||
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|||||||||||||||
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||||||||||||||
|
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Initial Value not specified
This register is defined in HDL source file impairment_correction.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..0 |
This value defines the group delay of the FIR filters based on the filter coefficients. It is used to delay the I path appropriately to match the Q path. |
Offset 0x0008: IINLINE_COEFF_REG Register (W) 🔗
|
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|||||||||||
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|||||||||||||||
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||||||||||||||
|
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Initial Value not specified
This register is defined in HDL source file impairment_correction.sv.
| Bits | Name |
| 31..25 |
Reserved |
| 24..0w |
Writing to this register will change the coefficient on the I inline path. The coefficient is of type Q2.23 (ARM notation), which means the value of 1.0 would be represented as 0x800000. (see https://en.wikipedia.org/wiki/Q_(number_format)#ARM_version) |
Offset 0x000C: ICROSS_COEFF_REG Register (W) 🔗
|
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|||||||||||
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|||||||||||||||
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||||||||||||||
|
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Initial Value not specified
This register is defined in HDL source file impairment_correction.sv.
| Bits | Name |
| 31..25 |
Reserved |
| 24..0w |
Writing to this register will shift the coefficient into the I cross FIR filter block. Update the coefficients in the order NUM_COEFFS-1 to 0. NUM_COEFFS write accesses are needed to update all coefficients. The coefficients are of type Q2.23 (ARM notation), which means the value of 1.0 would be represented as 0x800000. (see https://en.wikipedia.org/wiki/Q_(number_format)#ARM_version) |
Offset 0x0010: QINLINE_COEFF_REG Register (W) 🔗
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|||||||||||
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|||||||||||||||
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||||||||||||||
|
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Initial Value not specified
This register is defined in HDL source file impairment_correction.sv.
| Bits | Name |
| 31..25 |
Reserved |
| 24..0w |
Writing to this register will shift the coefficient into the Q inline FIR filter block. Update the coefficients in the order NUM_COEFFS-1 to 0. NUM_COEFFS write accesses are needed to update all coefficients. The coefficients are of type Q2.23 (ARM notation), which means the value of 1.0 would be represented as 0x800000. (see https://en.wikipedia.org/wiki/Q_(number_format)#ARM_version) |
JTAG_REGMAP 🔗
JTAG_REGS 🔗
This register map is present for each JTAG module.
Basic operation would be:
- poll ready until asserted
- write / read data
- write CONTROL register along with reset deasserted to start a transaction
For resetting the BITQ FSM, simply assert reset.
This operation seems a little strange, but it is what the axi_bitq driver expects. This behavior has been implemented in previous products.
Offset 0x0000: TX_DATA Register (W) 🔗
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|||||||||||
|
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Initial Value not specified
This register is defined in HDL source file ctrlport_to_jtag.v.
Data to be transmitted (TDI)
Offset 0x0004: STB_DATA Register (W) 🔗
|
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|
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|||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_jtag.v.
Data to be transmitted (TMS)
Offset 0x0008: CONTROL Register (R|W) 🔗
|
|
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|
|
|
|||||||||||
|
|
Initial Value = 0x00000001
This register is defined in HDL source file ctrlport_to_jtag.v.
JTAG module status and control
| Bits | Name |
| 31r |
Bitq FSM is ready for input (no data transmission in progress). |
| 31w | |
| 30..24 |
Reserved |
| 23..16 |
Reserved |
| 15..13 |
Reserved |
| 12..8 |
(Number of bits - 1) to be transferred |
| 7..0 |
Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value. |
Offset 0x000C: RX_DATA Register (R) 🔗
|
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|
|||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_jtag.v.
Received data (TDO)
LATTICE_RECONFIG_REGMAP 🔗
RECONFIG_REGISTERS 🔗
This regmap contains the registers to drive the wishbone interface of the EFB core.Offset 0x0000: WB_WRITE_REG Register (W) 🔗
|
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|
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|
|||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_regs.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..17 |
Reserved |
| 16w |
Set to 1 to issue a write command, set to 0 to issue a read command. |
| 15..8w |
Data in case of a write command. |
| 7..0w |
Address to access. |
Offset 0x0004: WB_READ_REG Register (R) 🔗
|
|
|
|
|
|
|
|||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_regs.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..17 |
Reserved |
| 16 |
Poll after issuing a read command until set to 1. |
| 15..8 |
Returned data from EFB core. Only valid if DATA_VALID is 1. |
| 7..0 |
Copy of WB_ADDR on read command. |
LED_CONTROL_REGMAP 🔗
LED_CONTROL_REGISTERS 🔗
This regmap contains the register to control all the HBX LEDs.Offset 0x0000: HBX_RF_LEDS (255:0) Register Array (R|W) 🔗
|
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|
|||||||||||||||
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|
|||||||||||||||||||||
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|
|||||||||||||||||
|
|
Intial Values
| default | => | 0x00000000 |
This register is defined in HDL source file led_control.sv.
It uses RegType HBX_RF_LEDS_TYPE which is
defined in HDL source file led_control.sv.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..14 |
Reserved |
| 13 |
Turn on the red LED for the RX LO port. |
| 12 |
Turn on the green LED for the RX LO port. |
| 11..10 |
Reserved |
| 9 |
Turn on the red LED for the TX LO port. |
| 8 |
Turn on the green LED for the TX LO port. |
| 7..5 |
Reserved |
| 4 |
Turn on the green LED for the RX port. |
| 3..2 |
Reserved |
| 1 |
Turn on the red LED for the TRX port. |
| 0 |
Turn on the green LED for the TRX port. |
Offset 0x0400: HBX_DEBUG_LEDS Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file led_control.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..4 |
Reserved |
| 3..0 |
CPLD_DEBUG_LED (initialvalue=0) Turn on the green debug LEDs. |
LO_PD_ADC_CONTROL_REGMAP 🔗
LO_PD_ADC_CONTROL_REGISTERS 🔗
Controls the SPI transaction to the LO Power Detector ADC ADS8862.Offset 0x0000: LO_PD_ADC_SPI_INFO Register (R) 🔗
Initial Value = 0x00000010
This register is defined in HDL source file lo_pd_adc_control.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
LO_PD_ADC_SPI_ADDR_WIDTH (initialvalue=0) The SPI transaction address width for the LO PD ADC is 0. The chip doesn't have any SPI addresses. |
| 7..0 |
LO_PD_ADC_SPI_DATA_WIDTH (initialvalue=16) The SPI transaction data width for the LO PD ADC is 16. |
Offset 0x0004: LO_PD_ADC_SPI_SETUP Register (W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file lo_pd_adc_control.sv.
| Bits | Name |
| 31w |
LO_PD_ADC_SPI_START_TRANSACTION (Strobe,initialvalue=0) Strobe this bit high to start the SPI transaction. |
| 30..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..0 |
Reserved |
Offset 0x0008: LO_PD_ADC_SPI_STATUS Register (R) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file lo_pd_adc_control.sv.
| Bits | Name |
| 31 |
LO_PD_ADC_SPI_READY (initialvalue=0) If this bit returns '1' then LO ADC is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. Poll this bit before starting an SPI transaction. |
| 30 |
LO_PD_ADC_SPI_DATA_VALID (initialvalue=0) Returns '1' when a read SPI transaction is complete.
If it returns '0' then it is busy with a previous SPI read. |
| 29..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
LO_PD_ADC_SPI_RD_DATA (initialvalue=0) Returns the data of the last SPI read. This bit field will retain it's old value until a new SPI read transaction has finished i.e. LO_PD_ADC_SPI_DATA_VALID returns '1'. |
LO_SYNTH_CONTROL_REGMAP 🔗
LO_SYNTH_CONTROL_REGISTERS 🔗
Controls the SPI transaction to the LMX2572Offset 0x0000: LO_SPI_INFO Register (R) 🔗
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Initial Value = 0x00000710
This register is defined in HDL source file lo_synth_control.sv.
| Bits | Name |
| 31..16 |
Elements available in the SPI queue. |
| 15..8 |
LO_SPI_ADDR_WIDTH (initialvalue=7) The SPI transaction address width for the LMX2572 is 7. |
| 7..0 |
LO_SPI_DATA_WIDTH (initialvalue=16) The SPI transaction data width for the LMX2572 is 16. |
Offset 0x0004: LO_SPI_SETUP Register (W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file lo_synth_control.sv.
| Bits | Name |
| 31w |
LO_SPI_START_TRANSACTION (Strobe,initialvalue=0) Strobe this bit high to start the SPI transaction. |
| 30w |
Set this bit to '1' to read from the LMX2572. Set this bit to '0' to write to the LMX2572. |
| 29..24 |
Reserved |
| 23 |
Reserved |
| 22..16w |
LO_SPI_WT_ADDR (initialvalue=0) Address of the LMX2572 |
| 15..0w |
LO_SPI_WT_DATA (initialvalue=0) Write Data to be sent to the LMX2572 |
Offset 0x0008: LO_SPI_STATUS Register (R) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file lo_synth_control.sv.
| Bits | Name |
| 31 |
If this bit returns '1' then LMX2572 is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. Poll this bit before starting an SPI transaction. |
| 30 |
LO_SPI_DATA_VALID (initialvalue=0) Returns '1' when a read SPI transaction is complete.
If it returns '0' then it is busy with a previous SPI read. |
| 29..24 |
Reserved |
| 23 |
Reserved |
| 22..16 |
LO_SPI_RD_ADDR (initialvalue=0) Returns the address (write or read) of the last SPI transaction. This bit field will retain it's old value until a new SPI transaction has finished. The value in here will be a copy of LO_SPI_WT_ADDR. |
| 15..0 |
LO_SPI_RD_DATA (initialvalue=0) Returns the data of the last SPI read. This bit field will retain it's old value until a new SPI read transaction has finished i.e. LO_SPI_DATA_VALID returns '1'. |
MB_CPLD_PL_REGMAP 🔗
This register map is available using the PL CPLD SPI interface. All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
MB_CPLD_PL_WINDOWS 🔗
Offset 0x0000: PL_REGISTERS Window (R|W) 🔗
Target regmap = PL_CPLD_BASE_REGMAP
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This window is defined in HDL source file mb_cpld.v.
Offset 0x0060: JTAG_DB0 Window (R|W) 🔗
Target regmap = JTAG_REGMAP
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This window is defined in HDL source file mb_cpld.v.
JTAG Master connected to first daugherboard's CPLD JTAG interface.
Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.
Offset 0x0080: JTAG_DB1 Window (R|W) 🔗
Target regmap = JTAG_REGMAP
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This window is defined in HDL source file mb_cpld.v.
JTAG Master connected to second daugherboard's CPLD JTAG interface.
Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.
NIXGE_REGMAP 🔗
XGE_MAC_REGS 🔗
nixge (maps to 10g mac if present)
Offset 0x0000: PORT_INFO Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
| Bits | Name |
| 31..24 |
Constant indicating version for this space. Not used by the NIXGE driver (12/4/2020) |
| 23..18 |
Reserved |
| 17 |
Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL. |
| 16 |
Generically means that a connection with a peer has been established. Specific meaning varies based on the MGT_PROTOCOL. |
| 15..8 |
Constant indicating what flavor of communication this port is using
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| 7..0 |
Constant indicating which port this register is hooked to
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Offset 0x0004: MAC_CTRL_STATUS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Definition of this register depends on Protocol
10GBE
READ - Status
- 0 = status_crc_error
- 1 = status_fragment_error
- 2 = status_txdfifo_ovflow
- 3 = status_txdfifo_udflow
- 4 = status_rxdfifo_ovflow
- 5 = status_rxdfifo_udflow
- 6 = status_pause_frame_rx
- 7 = status_local_fault
- 8 = status_remote_fault
WRITE - Ctl
- 0 = ctrl_tx_enable
100 GBE
READ - Status
- 0 = tx_ovfout - Sets if TX overflow reported by CMAC (Stays set till MAC is reset). This is a fatal error
- 1 = tx_unfout - Sets if TX underflow reported by CMAC (Stays set till MAC is reset). This is a fatal error
- 2 = stat_rx_aligned - goes high when CMAC has finished alignment, and is ready to start reception of traffic.
- 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID) but upstream is trying to hold(TREADY)off we drop a packet. Upstream circuitry should detect this when traffic is forked between CHDR and CPU, so this bit will only set if there is a HW design error.
- 4 = auto_config_done - This bit goes high when the auto_config state machine finishes operation. It is very similiar to stat_rx_alligned, but waits for extra writes which occur after allignement to complete.
- 24:16 = pause_mask - readable version of pause_mask bellow.
WRITE - Ctl
- 0 = auto_enable - Defaults to ON after reset - Enables a state machine that performs CMAC register writes to bring up the MAC without SW intervention.
- 24:16 = pause_mask - A second layer of enables(the first being register in the CMAC) on the pause_request mechanic. Bits 7:0 of enable pause on PFC7:0. Bit 8 enables global pause request (not priority controlled). The mask is used for TX and RX.
Offset 0x0008: MAC_PHY_STATUS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Definition of this register depends on Protocol
10GBE
*READ - Status *
- 0 = core_status 0 - link_up
- 1 = core_status 1
- 2 = core_status 2
- 3 = core_status 3
- 4 = core_status 4
- 5 = core_status 5
- 6 = core_status 6
- 7 = core_status 7
100 GBE
READ - Status
- 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
- 1 = usr_rx_reset - RX PLL's have locked
Offset 0x000C: MAC_LED_CTL Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1 |
When identify_enable is set, this value controls the activity LED. |
| 0 |
When set identify_value is used to control the activity LED. When clear the activity LED set on any TX or RX traffic to the mgt |
Offset 0x0010: ETH_MDIO_BASE Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
The x4xx family of products does not use MDIO.
Offset 0x0020: AURORA_OVERRUNS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
Offset 0x0024: AURORA_CHECKSUM_ERRORS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
Offset 0x0028: AURORA_BIST_CHECKER_SAMPS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
Offset 0x002C: AURORA_BIST_CHECKER_ERRORS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
XGE_MAC_WINDOW 🔗
Offset 0x1000: XGE_MAC Window (R|W) 🔗
Target regmap = XGE_MAC_REGMAP
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This window is defined in HDL source file uhd_regs.v.
PL_CPLD_BASE_REGMAP 🔗
MB_CPLD_LED_REGS 🔗
Register Map to control QSFP LEDs.Offset 0x0020: LED_REGISTER Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 15..12 |
Active LEDs of QSFP port 1 |
| 11..8 |
Link LEDs of QSFP port 1 |
| 7..4 |
Active LEDs of QSFP port 0 |
| 3..0 |
Link LEDs of QSFP port 0 |
PL_CMI_REGS 🔗
Cable present status register.Offset 0x0030: CABLE_PRESENT_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 1 |
Set to 1 if cable present in iPass 1 connector. |
| 0 |
Set to 1 if cable present in iPass 0 connector. |
PL_CPLD_BASE_REGS 🔗
Basic registers containing version and capabilities information.Offset 0x0000: SIGNATURE_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 31..0 |
Fixed value PL_CPLD_SIGNATURE of @.CONSTANTS_REGMAP |
Offset 0x0004: REVISION_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
Offset 0x000C: SCRATCH_REGISTER Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
Offset 0x0010: GIT_HASH_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
Value equals 0xDEADBEEF if the git hash was not used during synthesis.
| Bits | Name |
| 31..28 |
0x0 in case the git status was clean |
| 27..0 |
7 hex digit hash code of the commit |
PL_CPLD_REGMAP 🔗
This register map is available from the PS via AXI and MPM endpoint. Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.PL_CPLD_WINDOWS 🔗
Offset 0x0000: BASE Window (R|W) 🔗
Target regmap = CPLD_INTERFACE_REGMAP
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This window is defined in HDL source file cpld_interface.v.
Offset 0x8000: MB_CPLD Window (R|W) 🔗
Target regmap = MB_CPLD_PL_REGMAP
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This window is defined in HDL source file cpld_interface.v.
Offset 0x10000: DB0_CPLD Window (R|W) 🔗
Target regmap = X4XX_DB_SPI_REGMAP
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This window is defined in HDL source file cpld_interface.v.
Offset 0x18000: DB1_CPLD Window (R|W) 🔗
Target regmap = X4XX_DB_SPI_REGMAP
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This window is defined in HDL source file cpld_interface.v.
POWER_REGS_REGMAP 🔗
POWER_REGS_REGISTERS 🔗
This regmap contains the registers to control the HBX power supplies and the clock buffers for reference clocks.Offset 0x0000: RF_POWER_CONTROL Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file power_regs.sv.
During normal operation, all power supplies should be enabled.
| Bits | Name |
| 31..24 |
Reserved |
| 23..21 |
Reserved |
| 20 |
P8d7V_SMPS_EN (initialvalue=0) This positive 8.7V power supply sources the positive 8V. |
| 19 |
This positive 8V power source enables Tx amps. |
| 18 |
This positive 5.6V power supply sources the positive 5V. |
| 17 |
This positive 5V power source enables Tx LO amps. |
| 16 |
This positive 5V power source enables Rx LO amps. |
| 15 |
This positive 5V power source enables Tx RF and BB amps and switches. |
| 14 |
This positive 5V power source enables Rx RF and BB amps and switches. |
| 13 |
This positive 4V power supply sources all smaller (<4V) positive voltages. |
| 12 |
P3d3V_ADMV1320_EN (initialvalue=0) This positive 3.3V power source enables the ADMV1320 upconverter (Tx). |
| 11 |
P3d3V_ADMV1420_EN (initialvalue=0) This positive 3.3V power source enables the ADMV1420 downconverter (Rx). |
| 10 |
P3d3V_RX_BB_AMP1_EN (initialvalue=0) This positive 3.3V power source enables Rx BB amps. |
| 9 |
P3d3V_RX_BB_AMP2_EN (initialvalue=0) This positive 3.3V power source enables Rx BB amps. |
| 8 |
P3d3V_TX1_LO1_EN (initialvalue=0) This positive 3.3V power source enables the Tx LO Synthesizer, DSAs and RF Switches. |
| 7 |
P3d3V_RX1_LO1_EN (initialvalue=0) This positive 3.3V power source enables the Rx LO Synthesizer, DSAs and RF Switches. |
| 6 |
P3d3V_REF_CLK_EN (initialvalue=0) This positive 3.3V power source enables the PLL Reference Clock coming from the X400 motherboard for the entire HBX daughterboard. |
| 5 |
This positive 3.3V power source enables the Tx and Rx DSAs and RF Switches. |
| 4 |
P2d5V_TX_BB_AMP_EN (initialvalue=0) This positive 2.5V power source enables Tx BB amps. |
| 3 |
This negative 3.3V power source enables the Tx and Rx LO. |
| 2 |
This negative 3.2V power supply sources the negative 2.5V and negative 1.7V. |
| 1 |
This negative 2.5V power source enables the Tx and Rx BB including amps and RF switches. |
| 0 |
This negative 1.7V power source enables the Rx BB including amps. |
Offset 0x0004: RF_POWER_STATUS Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file power_regs.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..11 |
Reserved |
| 10 |
Returns the status of the positive 8.7V power supply. |
| 9 |
Returns the status of the positive 8V for Tx amps. |
| 8 |
Returns the status of the positive 5.6V power supply. |
| 7 |
Returns the status of the positive 4V power supply. |
| 6 |
Returns the status of the positive 3.3V for ADMV1320. |
| 5 |
Returns the status of the positive 3.3V for ADMV1420. |
| 4 |
Returns the status of the negative 3.3V Tx LDO. |
| 3 |
Returns the status of the negative 3.3V Rx LDO. |
| 2 |
Returns the status of the negative 3.2V power supply. |
| 1 |
Returns the status of the negative 2.5V for the Tx and Rx BB amps and RF switches. |
| 0 |
Returns the status of the negative 1.7V for the Rx BB amps. |
Offset 0x0008: CPLD_INTERNAL_REG Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file power_regs.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1 |
In order to avoid any damage to the ICs on the daughterboard, this bit should be set
after all power rails are properly turned on. |
| 0 |
PLL_REF_CLOCK_ENABLE (initialvalue=0) This bitfield controls the PLL Reference Clock used within the DB CPLD for most
functionality like the FPGA GPIO communication and all IO's facing ICs in the RF
paths. |
PS_CPLD_BASE_REGMAP 🔗
DIO_REGS 🔗
Registers to control the GPIO buffer direction on the DIO board connected to the FPGA. Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. Set the direction in the FPGA's DIO register appropriately.Offset 0x0030: DIO_DIRECTION_REGISTER Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file ps_cpld_regs.v.
Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
PS_CMI_REGS 🔗
Cable present status register.Offset 0x0034: SERIAL_NUM_LOW_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
Offset 0x0038: SERIAL_NUM_HIGH_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
Offset 0x003C: CMI_CONTROL_STATUS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31r |
1 if an upstream CMI device has been detected. |
| 30..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Set if the device is ready to establish a PCI-Express link (affects CMI_CLP_READY bit). |
PS_CONTROL_REGS 🔗
Register Map to control MB CPLD functions.Offset 0x0020: PL_DB_REGISTER Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..22 |
Reserved |
| 21w |
Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1) |
| 20w |
Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0) |
| 19..18 |
Reserved |
| 17w |
Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1) |
| 16w |
Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0) |
| 15 |
Reserved |
| 14w |
Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock. |
| 13w |
Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1) |
| 12w |
Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0) |
| 11 |
Reserved |
| 10w |
Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK) |
| 9w |
Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1) |
| 8w |
Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0) |
| 7..6 |
Reserved |
| 5r |
Indicates that reset is asserted for DB 1. |
| 4r |
Indicates that reset is asserted for DB 0. |
| 3 |
Reserved |
| 2r |
Indicates if the PLL reference clock for the PL interface is enabled. |
| 1r |
Indicates if a clock is forwarded to DB 1. |
| 0r |
Indicates if a clock is forwarded to DB 0. |
PS_CPLD_BASE_REGS 🔗
Basic registers containing version and capabilites information.Offset 0x0000: SIGNATURE_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..0 |
Fixed value PS_CPLD_SIGNATURE of @.CONSTANTS_REGMAP |
Offset 0x0004: REVISION_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
Offset 0x000C: SCRATCH_REGISTER Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
Offset 0x0010: GIT_HASH_REGISTER Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
Value equals 0xDEADBEEF if the git hash was not used during synthesis.
| Bits | Name |
| 31..28 |
0x0 in case the git status was clean |
| 27..0 |
7 hex digit hash code of the commit |
PS_POWER_REGMAP 🔗
PS_POWER_REGS 🔗
Registers to control power supplies on the motherboard.Offset 0x0000: IPASS_POWER_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_power_regs.v.
| Bits | Name |
| 31r |
Asserted signal indicates a power fault in power switch for iPass connector 1. Sticky bit. Asserted on occurrence. Reset using IPASS_CLEAR_POWER_FAULT1. |
| 31w |
Clear IPASS_POWER_FAULT1. |
| 30r |
Asserted signal indicates a power fault in power switch for iPass connector 0. Sticky bit. Asserted on occurrence. Reset using IPASS_CLEAR_POWER_FAULT0. |
| 30w |
Clear IPASS_POWER_FAULT0. |
| 29..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Set to 1 to disable power for both iPass connectors. |
Offset 0x0004: OSC_POWER_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file ps_power_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1 |
Enables 5V power switch for the 122.88 MHz oscillator. |
| 0 |
Enables 5V power switch for the 100 MHz oscillator. |
QSFP_REGMAP 🔗
QSFP_WINDOWS 🔗
Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations
- 1X10GB Ethernet - Using OpenCore XGE MAC
- 1x100GB Ethernet - Using Xilinx CMAC
- (future possible) - Xilinx Aurora (various rates and lane widths)
- (future possible) - 4X10GB Ethernet
Offset 0x0000: ETH_DMA Window (R|W) 🔗
Target regmap = DMA_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0x8000: NIXGE Window (R|W) 🔗
Target regmap = NIXGE_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0xA000: UIO Window (R|W) 🔗
Target regmap = UIO_REGMAP
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This window is defined in HDL source file uhd_regs.v.
Offset 0xC000: CMAC Window (R|W) 🔗
Target regmap = CMAC_REGMAP
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This window is defined in HDL source file uhd_regs.v.
RADIO_CTRLPORT_REGMAP 🔗
RADIO_CTRLPORT_WINDOWS 🔗
Each radio's CtrlPort peripheral interface is divided into the following memory spaces. Note that the CtrlPort peripheral interface starts at offset 0x80000 in the RFNoC Radio block's register space. The following diagram displays the distribution of the CtrlPort interface to the different modules it interacts with.
Offset 0x0000: DB_WINDOW Window (R|W) 🔗
Target regmap = DB_WINDOW_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0x8000: RFDC_TIMING_WINDOW Window (R|W) 🔗
Target regmap = RFDC_TIMING_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0xA000: RF_CORE_WINDOW Window (R|W) 🔗
Target regmap = RF_CORE_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0xC000: DIO_WINDOW Window (R|W) 🔗
Target regmap = RADIO_DIO_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
RADIO_DIO_REGMAP 🔗
This map contains register windows for controlling the different sources that drive the state of DIO lines.DIO_SOURCES 🔗
Offset 0x0000: RADIO_GPIO_ATR_REGS Window (R|W) 🔗
Target regmap = GPIO_ATR_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0x1000: DIO_SOURCE_CONTROL Window (R|W) 🔗
Target regmap = DIO_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
Offset 0x2000: DIGITAL_IFC_REGS Window (R|W) 🔗
Target regmap = DIG_IFC_REGMAP
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This window is defined in HDL source file x4xx_core_common.v.
RECONFIG_REGMAP 🔗
RECONFIG_REGS 🔗
These registers are used to upload and verify a new primary image to the Max 10 FPGA on-chip flash when configured to support dual configuration images. The steps below outline the process of verifying/preparing the new image to be written, erasing the current image, writing the new image, and verifying the new image was successfully written.Prepare the data...
The Max 10 FPGA build should generate a *cfm0_auto.rpd file The *.rpd file is a "raw programming data" file holding all data related to the configuration image (CFM0). There are two important items to note regarding the addresses. First the *rpd data uses byte addresses. Second, the start/end addresses defined by FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses
As a sanity check, verify the size of the raw programming data for CFM0 correspond to the address range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by reading the values from FLASH_CFM0_START_ADDR_REG and FLASH_CFM0_END_ADDR, subtract both values, add one and multiply by four.
Having passed the sanity check the *.rpd data must now be manipulated into the form required by Altera's on-chip flash IP. Two operations must be performed. First the data must be converted from bytes to 32-bit words. Second the bit order must be reversed. This is illustrated in in the following table which shows byte address and data from the *.rpd file compared to the word address and data to be written to the on-chip flash.
.Map Addr .Map Data Flash Addr Flash Data 0x2B800 0x01 0xAC00 0x8040C020 0x2B801 0x02 0x2B802 0x03 0x2B803 0x04 0x2B804 0x05 0xAC01 0xA060E010 0x2B805 0x06 0x2B806 0x07 0x2B807 0x08 The resulting set of flash address data pairs should be used when writing FLASH_ADDR_REG and FLASH_WRITE_DATA_REG to update the CFM0 image. However, prior to writing the new image the old image must be erased.
Erase the current primary flash image...
- Read FLASH_STATUS_REG and verify no error bits are asserted and that all read, write, and erase operations are idle.
- Disable write protection of the flash by strobing the FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.
- Verify write protection is disabled and no errors are present by reading FLASH_STATUS_REG.
- Initiate the erase operation by setting FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of FLASH_CONTROL_REG.
- Poll the FLASH_ERASE_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the erase operation is complete, then verify the operation was successful by checking that the FLASH_ERASE_ERR bit is de-asserted. Erase operations are expected to take a maximum of 350 msec. Upon completion of the erase operation write protection will remain disabled.
- Erase additional sectors as required (see FLASH_ERASE_SECTOR for details) by restarting with first step.
Write the new primary flash image...
- Read FLASH_STATUS_REG and verify no error bits are asserted, all read, write, and erase operations are idle, and write protection is disabled.
- Set the target address for the write to the Max 10 on-chip flash by writing value from FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
- Set the data to be written to this address by writing the new 32-bit word of the new image to FLASH_WRITE_DATA_REG.
- Initiate the write by strobing FLASH_WRITE_STB of FLASH_CONTROL_REG.
- Poll the FLASH_WRITE_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the write operation is complete, then verify the operation was successful by checking that the FLASH_WRITE_ERR bit is de-asserted. Write operations are expected to take a maximum of 550 usec.
- Upon completion of the write operation return to step 2, incrementing the target address by one, and writing the next 32-bit word to Max10FlashWriteDatReg. If this was the last write, indicated by writing to FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step to enable write protection.
- After writing the new image enable write protection by strobing the FLASH_ENABLE_WP_STB bit of FLASH_CONTROL_REG.
Verify the new primary flash image...
- Read FLASH_STATUS_REG and verify no error bits are asserted and that all read, write, and erase operations are idle.
- Set the target address for the read in the Max 10 on-chip flash by writing value from FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.
- Initiate the read by strobing FLASH_READ_STB of FLASH_CONTROL_REG.
- Poll the FLASH_READ_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the read operation is complete, then verify the operation was successful by checking that the FLASH_READ_ERR bit is de-asserted. There is no guidance on exactly how long reads take to complete, but they are expected to be fairly quick. A very conservative timeout on this polling would be similar to that used for write operations.
- Upon completion of the read operation the resulting data returned by the on-chip flash will be available in Max10FlashReadDatReg. Read this register, compare to expected value previously written, and ensure they match.
- Return to step 2, incrementing the target address by one. If this was the last read verification is complete and no further action is required.
After the flash has been erased, programmed, and verified, a power cycle is required for the new image to become active.
FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration 🔗
These values are the start and end address of the CFM image flash sector from Intel's On-Chip Flash IP Generator. Be aware that three different values exist per each of the two supported MAX10 variants: 10M04 and 10M08 Note that the values given in the IP generator are byte based where the values of this enum are U32 based (divided by 4).| Value | Name | |
| Dec | Hex | |
| 4096 | 0x01000 | |
| 8192 | 0x02000 | |
| 39936 | 0x09C00 | |
| 44032 | 0x0AC00 | |
| 75775 | 0x127FF | |
| 79871 | 0x137FF | |
This enumerated type is defined in HDL source file reconfig_engine.v.
Offset 0x0000: FLASH_STATUS_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..17 |
Reserved |
| 16 |
This bit is asserted when the flash can hold an image with memory initialization. |
| 15..14 |
Reserved |
| 13 |
This bit is asserted when write operation fails. Clear this error by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In the event of a write error... |
| 12 |
This bit is de-asserted when a write operation is in progress. Poll this bit after strobing the FLASH_WRITE_STB bit of FLASH_CONTROL_REG to determine when the write operation has completed, then check the FLASH_WRITE_ERR bit to verify the operation was successful. |
| 11..10 |
Reserved |
| 9 |
This bit is asserted when an erase operation fails. Clear this error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In the event of an erase error... |
| 8 |
This bit is de-asserted when an erase operation is in progress. Poll this bit after strobing the FLASH_ERASE_STB bit of FLASH_CONTROL_REG to determine when the erase operation has completed, then check the FLASH_ERASE_ERR bit to verify the operation was successful. |
| 7..6 |
Reserved |
| 5 |
This bit is asserted when a read operation fails. Clear this error by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the event of a read error... |
| 4 |
This bit is de-asserted when a read operation is in progress. Poll this bit after strobing the FLASH_READ_STB bit of FLASH_CONTROL_REG to determine when the read operation has completed, then check the FLASH_READ_ERR bit to verify the operation was successful. |
| 3..1 |
Reserved |
| 0 |
This bit is asserted when the flash is write protected and de-asserted when write protection is disabled. |
Offset 0x0004: FLASH_CONTROL_REG Register (W) 🔗
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Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..11 |
Reserved |
| 10w |
CLEAR_FLASH_ERASE_ERROR_STB (Strobe) Strobe this bit to clear an erase error. |
| 9w |
CLEAR_FLASH_WRITE_ERROR_STB (Strobe) Strobe this bit to clear a write error. |
| 8w |
CLEAR_FLASH_READ_ERROR_STB (Strobe) Strobe this bit to clear a read error. |
| 7..5w |
Defines the sector to be erased. Has to be set latest with the
write access which starts the erase operation by strobing
FLASH_ERASE_STB. |
| 4w |
Strobe this bit to erase the primary Max10 configuration image (CFM0). |
| 3w |
Strobe this bit to write the data contained in FLASH_WRITE_DATA_REG to the flash address identified in FLASH_ADDR_REG. |
| 2w |
Strobe this bit to read data from the flash address identified in FLASH_ADDR_REG. |
| 1w |
Strobe this bit to disable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). |
| 0w |
Strobe this bit to enable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). |
Offset 0x0008: FLASH_ADDR_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..17 |
Reserved |
| 16..0 |
This field holds the target address for the next read or write operation. Set this field prior to strobing the FLASH_WRITE_STB and FLASH_READ_STB bits of FLASH_CONTROL_REG. Valid addresses are defined by the FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration. |
Offset 0x000C: FLASH_WRITE_DATA_REG Register (W) 🔗
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Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0w |
Data in this register will be written to the flash at the address identified in FLASH_ADDR_REG when a successful write operation is executed. |
Offset 0x0010: FLASH_READ_DATA_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0 |
This register contains data read from the flash address identified in FLASH_ADDR_REG after a successful read operation is executed. |
Offset 0x0014: FLASH_CFM0_START_ADDR_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0 |
Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). |
Offset 0x0018: FLASH_CFM0_END_ADDR_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0 |
Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). |
RF_SWITCHES_REGMAP 🔗
RX_SWITCHES 🔗
This regmap contains the switches in RX data path from RF antenna to MB connector in bit range 0-15 and the switches for the RX LO path in bit range 16-31.Offset 0x0400: RX_SW_REG (255:0) Register Array (R|W) 🔗
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Intial Values
| default | => | 0x00000000 |
This register is defined in HDL source file switches.sv.
It uses RegType RX_SW_REG_TYPE which is
defined in HDL source file switches.sv.
| Bits | Name |
| 31..30 |
RX_LO_SBHM_FB (initialvalue=0) Selects the appropriate subharmonic filter path for RX LO band 2/3: filter 3 (0), filter 4 (1), filter 5 (2), filter 6 (3). |
| 29..28 |
Selects the appropriate filter path for RX LO band 1: F4 (0), F1 (1), F2 (2), F3 (3). |
| 27 |
Reserved |
| 26 |
RX_LO_B23_SW2 (initialvalue=0) Drives RX LO band 2/3 signal into band 2 (0) or band 1 (1). |
| 25 |
RX_LO_B23_SW1 (initialvalue=0) Selects pre-doubler filter 2 (0) or pre-doubler filter 1 (1) as input for RX LO band 2/3. |
| 24 |
Selects LO Band 1 LF (0) or LO Band 1 HF (1) path for LTC input. |
| 23..22 |
Reserved |
| 21..20 |
Connects the RX LO input path with band 1 (0), band 1/2 pre-doubler filter 2 (1), band 1/2 pre-doubler filter 1 (2) or power detector (3). |
| 19..17 |
Reserved |
| 16 |
Selects the LO source for internal RX RF path. 0 = internal synthesizer, 1 = RX LO In port. |
| 15..14 |
Connects to one of 4 options: |
| 13 |
Selects the LF path from RF antenna to Band 0 (0) or the ADMV chip (1). |
| 12 |
Selects the direct path from RF antenna to MB connector (1) or the IQ path with the LTC (0). |
| 11 |
RX_DIRECT_SW1 (initialvalue=0) Selects the path from RF antenna to MB connector (0) or the MB Sync Injection (1). |
| 10 |
Output selection between the 8 filters from RX_B1_SW4 (1) and filter number 9 (0) coming from RX_B1_SW2. |
| 9..7 |
This switch is located at the output of the Band 1 filter bank. |
| 6..4 |
This switch sits at the input of the Band 1 filter bank. |
| 3 |
Reserved |
| 2 |
Input selection between the 8 filters from RX_B1_SW3 (0) and filter number 9 (1). |
| 1 |
Switch between band 0 (1) and the ADMV chip (0) as band 1 input path. |
| 0 |
Directs the IQ stream from Band 1 (0) or Band 2 (1) into motherboard. |
TX_SWITCHES 🔗
This regmap contains the switches in TX data path from MB connector to RF antenna in bit range 0-15 and the switches for the TX LO path in bit range 16-31.Offset 0x0000: TX_SW_REG (255:0) Register Array (R|W) 🔗
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Intial Values
| default | => | 0x00000000 |
This register is defined in HDL source file switches.sv.
It uses RegType TX_SW_REG_TYPE which is
defined in HDL source file switches.sv.
| Bits | Name |
| 31..30 |
TX_LO_SBHM_FB (initialvalue=0) Selects the appropriate filter path for TX LO band 2/3. |
| 29..28 |
Selects the appropriate filter path for TX LO band 1. |
| 27..26 |
Reserved |
| 25 |
TX_LO_B23_SW2 (initialvalue=0) Drives TX LO band2/3 signal into band 2 (0) or band 3 (1). |
| 24 |
TX_LO_B23_SW1 (initialvalue=0) Selects filter 2 (0) or filter 1 (1) as input for TX LO band 2/3. |
| 23..22 |
Reserved |
| 21..20 |
Connects the TX LO input path with band 1 (0), band 2/3 filter 2 (1), band 2/3 filter 1 (2) or power detector (3). |
| 19..17 |
Reserved |
| 16 |
Selects the LO source for internal TX RF path. 0 = internal synthesizer, 1 = TX LO In port. |
| 15 |
Connects RF antenna to TX (0) or RX (1) path. |
| 14 |
TX_RF_SW_LOOP (initialvalue=0) Connect TX RF Path from TX_RF_SW_LF to antenna (1) or RX Loopback path (0). |
| 13 |
Selects ADMV output = Band 2 or 3 (1) or output of low frequency path = Band 0 or 1 depending on TX_LF_SW1 (0) for the TX RF path. |
| 12 |
Selects Band 0 (0) or Band 1 (1) for the low frequency path. |
| 11 |
Reserved |
| 10..8 |
This switch is located at the output of the Band 1 filter bank. |
| 7 |
Reserved |
| 6..4 |
This switch sits at the input of the Band 1 filter bank. |
| 3..2 |
Reserved |
| 1 |
Directs the IQ stream from TX_BB_SW1 into Band 2 (0) or Band 3 (1). |
| 0 |
Directs the IQ stream from motherboard into Band 1 (0) or further splitting by TX_BB_SW2 (1). |
RFDC_REGS_REGMAP 🔗
RFDC_REGS 🔗
These are the registers located within the RFDC block design that provide control and status support for the RF chain.FABRIC_DSP_BW_ENUM Enumeration 🔗
| Value | Name | |
| Dec | Hex | |
| 0 | 0x000 | |
| 100 | 0x064 | |
| 200 | 0x0C8 | |
| 400 | 0x190 | |
| 1000 | 0x3E8 | |
This enumerated type is defined in HDL source file common_regs.v.
RFDC_BLOCK_INFO_ENUM Enumeration 🔗
| Value | Name | |
| Dec | Hex | |
| 0 | 0x0 | |
| 1 | 0x1 | |
| 2 | 0x2 | |
| 3 | 0x3 | |
This enumerated type is defined in HDL source file rfdc_info_pkg.sv.
Offset 0x0000: MMCM Window (R|W) 🔗
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This window is defined in HDL source file x420_rfdc_regs.v.
Offset 0x10000: INVERT_DB0_IQ_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..12 |
Reserved |
| 11 | |
| 10 | |
| 9 | |
| 8 | |
| 7..4 |
Reserved |
| 3 | |
| 2 | |
| 1 | |
| 0 |
Offset 0x10800: INVERT_DB1_IQ_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..12 |
Reserved |
| 11 | |
| 10 | |
| 9 | |
| 8 | |
| 7..4 |
Reserved |
| 3 | |
| 2 | |
| 1 | |
| 0 |
Offset 0x11000: MMCM_RESET_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Write a '1' to this bit to reset the MMCM. Then write a '0' to place the MMCM out of reset. |
Offset 0x12000: RF0_RESET_CONTROL_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType RF_RESET_CONTROL_REGTYPE which is
defined in HDL source file common_regs.v.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..11 |
Reserved |
| 10 |
Write a '1' to this bit to trigger a reset for the DAC gearboxes. There is no done signal for this reset. |
| 9 |
Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted. |
| 8 |
Write a '1' to this bit to trigger a reset for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted. |
| 7 |
Reserved |
| 6 |
Write a '1' to this bit to trigger a reset for the ADC gearboxes. There is no done signal for this reset. |
| 5 |
Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted. |
| 4 |
Write a '1' to this bit to trigger a reset for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted. |
| 3..1 |
Reserved |
| 0 |
Write a '1' to this bit to reset the RF reset controller. Write a '0' once db0_fsm_reset_done asserts. |
Offset 0x12008: RF0_RESET_STATUS_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType RF_RESET_STATUS_REGTYPE which is
defined in HDL source file common_regs.v.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..12 |
Reserved |
| 11 |
This bit asserts ('1') when the DB0 DAC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset). |
| 10..8 |
Reserved |
| 7 |
This bit asserts ('1') when the DB0 ADC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset). |
| 6..4 |
Reserved |
| 3 |
This bit asserts ('1') when the DB0 RF reset controller FSM reset sequence is completed. The bitfield deasserts ('0') after deasserting db0_fsm_reset. |
| 2..0 |
Reserved |
Offset 0x12800: RF1_RESET_CONTROL_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType RF_RESET_CONTROL_REGTYPE which is
defined in HDL source file common_regs.v.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..11 |
Reserved |
| 10 |
Write a '1' to this bit to trigger a reset for the DAC gearboxes. There is no done signal for this reset. |
| 9 |
Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted. |
| 8 |
Write a '1' to this bit to trigger a reset for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted. |
| 7 |
Reserved |
| 6 |
Write a '1' to this bit to trigger a reset for the ADC gearboxes. There is no done signal for this reset. |
| 5 |
Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted. |
| 4 |
Write a '1' to this bit to trigger a reset for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted. |
| 3..1 |
Reserved |
| 0 |
Write a '1' to this bit to reset the RF reset controller. Write a '0' once db0_fsm_reset_done asserts. |
Offset 0x12808: RF1_RESET_STATUS_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType RF_RESET_STATUS_REGTYPE which is
defined in HDL source file common_regs.v.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..12 |
Reserved |
| 11 |
This bit asserts ('1') when the DB0 DAC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset). |
| 10..8 |
Reserved |
| 7 |
This bit asserts ('1') when the DB0 ADC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset). |
| 6..4 |
Reserved |
| 3 |
This bit asserts ('1') when the DB0 RF reset controller FSM reset sequence is completed. The bitfield deasserts ('0') after deasserting db0_fsm_reset. |
| 2..0 |
Reserved |
Offset 0x13000: RF_AXI_STATUS_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType RF_AXI_STATUS_REGTYPE which is
defined in HDL source file common_regs.v.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.
| Bits | Name |
| 31..30 |
This bitfield is wired to the user's ADC (DB1) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 29..28 |
This bitfield is wired to the user's ADC (DB1) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 27..26 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TValid handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 25..24 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TValid handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 23..22 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TReady handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 21..20 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TReady handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 19..18 |
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 17..16 |
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 15..14 |
This bitfield is wired to the user's ADC (DB0) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 13..12 |
This bitfield is wired to the user's ADC (DB0) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 11..10 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TValid handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 9..8 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TValid handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 7..6 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TReady handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 5..4 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TReady handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 3..2 |
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 1..0 |
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
Offset 0x13008: FABRIC_DSP_REG Register (R) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType FABRIC_DSP_REGTYPE which is
defined in HDL source file common_regs.v.
The X410 platform supports multiple RF daughterboards, each requiring a different fabric RF DSP chain that works with specific RFDC settings. Each bandwidth DSP chain has a unique identifier (BW in MHz), this information is conveyed in this register to let the driver configure the RFDC with the proper settings. Also, channel count for the DSP module is included.
Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.
| Bits | Name |
| 31..20 |
FABRIC_DSP_BW (initialvalue=FABRIC_DSP_BW_NONE) Fabric DSP BW in MHz for both daughterboards. The values for this bitfield are in the FABRIC_DSP_BW_ENUM table. (show herehide) |
| 19..18 |
FABRIC_DSP_RESERVED_DB1 (initialvalue=0) Reserved for future use. |
| 17..14 |
FABRIC_DSP_TX_CNT_DB1 (initialvalue=0) Fabric DSP TX channel count for daughterboard 0. |
| 13..10 |
FABRIC_DSP_RX_CNT_DB1 (initialvalue=0) Fabric DSP RX channel count for daughterboard 0. |
| 9..8 |
FABRIC_DSP_RESERVED (initialvalue=0) Reserved for future use. |
| 7..4 |
FABRIC_DSP_TX_CNT (initialvalue=0) Fabric DSP TX channel count for daughterboard 0. |
| 3..0 |
FABRIC_DSP_RX_CNT (initialvalue=0) Fabric DSP RX channel count for daughterboard 0. |
Offset 0x14000: CALIBRATION_DATA Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..16 | |
| 15..0 |
Offset 0x14008: CALIBRATION_ENABLE Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7 |
Enables calibration data for channel #1/3. |
| 6 |
Enables calibration data for channel #1/2. |
| 5 |
Enables calibration data for channel #1/1. |
| 4 |
Enables calibration data for channel #1/0. |
| 3 |
Enables calibration data for channel #0/3. |
| 2 |
Enables calibration data for channel #0/2. |
| 1 |
Enables calibration data for channel #0/1. |
| 0 |
Enables calibration data for channel #0/0. |
Offset 0x15000: THRESHOLD_STATUS Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15 | |
| 14 | |
| 13 | |
| 12 | |
| 11 | |
| 10 | |
| 9 | |
| 8 | |
| 7 | |
| 6 | |
| 5 | |
| 4 | |
| 3 | |
| 2 | |
| 1 | |
| 0 |
Offset 0x16000: RF_PLL_CONTROL_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..25 |
Reserved |
| 24 | |
| 23..21 |
Reserved |
| 20 | |
| 19..17 |
Reserved |
| 16 | |
| 15..13 |
Reserved |
| 12 | |
| 11..9 |
Reserved |
| 8 | |
| 7..0 |
Reserved |
Offset 0x16008: RF_PLL_STATUS_REG Register (R) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..21 |
Reserved |
| 20 | |
| 19..17 |
Reserved |
| 16 | |
| 15..8 |
Reserved |
| 7..0 |
Reserved |
Offset 0x17000: RFDC_INFO_MEM (15:0) Register Array (R) 🔗
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Initial Value not specified
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType RFDC_INFO_MEMTYPE which is
defined in HDL source file rfdc_info_pkg.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..12 |
Reserved |
| 11 |
If the converter is an ADC this bit is set. Otherwise it is an DAC. |
| 10 |
DB index. |
| 9..8 |
Index of the RFNoC channel per DB. |
| 7..6 |
If there are multiple physical paths per RFNoC channel this index is used to separate them. I/Q converters linked together should share the same subchannel index. |
| 5..4 |
Zero based tile offset of the FPGA. For DAC index i equals to FPGA tile 228+i. For ADC index i equals to FPGA tile 224+i. |
| 3..2 |
Index of the ADC/DAC within the FPGA tile. |
| 1..0 |
The mixer setting of this ADC/DAC. The values for this bitfield are in the RFDC_BLOCK_INFO_ENUM table. (show herehide) |
Offset 0x18000: RFDC_INFO_REG Register (R) 🔗
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Initial Value = 0x00910091
This register is defined in HDL source file x420_rfdc_regs.v.
It uses RegType RFDC_INFO_REGTYPE which is
defined in HDL source file common_regs.v.
Specifically, between the actual RFDC and the RFNoC infrastructure, there may be additional resampling (if the RFDC resampler cannot handle all the resampling itself) and it is important to know how wide the connection from the RFDC gearbox FIFO to the rest of the design is. Note: The *_DB1 constants are not used in the HDL, their purpose is merely for documentation.
| Bits | Name |
| 31..26 |
Reserved |
| 25..23 |
RFDC_INFO_SPC_TX_DB1 (initialvalue=1) Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1. |
| 22..20 |
RFDC_INFO_SPC_RX_DB1 (initialvalue=1) Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1. |
| 19..16 |
RFDC_INFO_XTRA_RESAMP_DB1 (initialvalue=1) Additional resampling happening outside the RFDC for daughterboard 0. |
| 15 |
RFDC_CLK_DIV4_ENABLE (initialvalue=0) This flag applies to X410 only. RFDC clock in PS block diagram gets divided by 4 if this flag is set. The resulting ratio between rfdc_clk and rfdc_clk2x is 1:8. |
| 14..10 |
Reserved |
| 9..7 |
RFDC_INFO_SPC_TX (initialvalue=1) Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0. |
| 6..4 |
RFDC_INFO_SPC_RX (initialvalue=1) Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0. |
| 3..0 |
RFDC_INFO_XTRA_RESAMP (initialvalue=1) Additional resampling happening outside the RFDC for daughterboard 0. |
RFDC_TIMING_REGMAP 🔗
RFDC_TIMING_REGS 🔗
Offset 0x0000: NCO_RESET_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file rfdc_timing_control.sv.
| Bits | Name |
| 31..25 |
Reserved |
| 24w |
Enables writing to the SYSREF_WAIT bitfield |
| 23..16 |
Sets the number of sysref cycles to wait before resuming NCO operation after reset. DB0 will take priority if more than one db is setting this value. |
| 15..9 |
Reserved |
| 8r |
When 1, indicates that the NCO reset failed to complete in the expected time. |
| 7..2 |
Reserved |
| 1r |
When 1, indicates that the NCO reset has completed. |
| 0w |
Write a 1 to this bit to start the RFDC's NCO reset state machine. |
Offset 0x0004: GEARBOX_RESET_REG Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file rfdc_timing_control.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1w |
This reset is for the gearbox on the DAC data path that is used to move data from one clock domain to another outside the RFDC. Write a 1 to this bit to send a reset pulse to the DAC gearbox. |
| 0w |
This reset is for the gearbox on the ADC data path that is used to move data from one clock domain to another outside the RFDC. Write a 1 to this bit to send a reset pulse to the ADC gearbox. |
RX_RF_PD_REGMAP 🔗
RX_RF_PD_REGISTERS 🔗
Provides control and status registers for the RX_RF_PD circuit.Offset 0x0000: RX_RF_PD_THRESHOLD Register (R|W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file rx_rf_pd.sv.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
RX_RF_PD_THRESHOLD_VALUE (initialvalue=0) This value sets the threshold level for the RX RF Power Detector. The value is a 16-bit unsigned integer, with values going from 0V up to 2.5V. One bit is worth ~38uV. |
Offset 0x0004: RX_RF_PD_CONTROL Register (W) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file rx_rf_pd.sv.
This fields in this register are write-only strobe bits.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..3 |
Reserved |
| 2w |
RX_RF_PD_OVERLOAD_RESET (Strobe,initialvalue=0) Writing a '1' to this bit will reset the overload flag in the RX_RF_PD_OVERLOAD register. |
| 1w |
RX_RF_PD_CONTROL_DISABLE (Strobe,initialvalue=0) Disables the RX RF Power Detector control loop. (Overrides RX_RF_PD_CONTROL_ENABLE) |
| 0w |
RX_RF_PD_CONTROL_ENABLE (Strobe,initialvalue=0) Enables the RX RF Power Detector control loop. (May be overwritten by RX_RF_PD_CONTROL_DISABLE) |
Offset 0x0008: RX_RF_PD_STATUS Register (R) 🔗
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Initial Value = 0x00000000
This register is defined in HDL source file rx_rf_pd.sv.
This includes if the PD control loop is currently running, the current overload status, and the current power value read from the ADC.
| Bits | Name |
| 31 |
RX_RF_PD_CONTROL_RUNNING (initialvalue=0) Indicates if the RX RF Power Detector control loop is currently running. '1' indicates that the control loop is active, '0' indicates it is disabled. |
| 30 |
RX_RF_PD_OVERLOAD (initialvalue=0) This sticky bit indicates if any overload condition has been detected since the last reset
of this overload flag.
'1' indicates that an overload has occurred, '0' indicates no overloads have been detected. |
| 29..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
RX_RF_PD_ADC_VALUE (initialvalue=0) This value reflects the most recent power level read from the RX RF Power Detector ADC. The value is a 16-bit unsigned integer, with values going from 0V up to 2.5V. One bit is worth ~38uV. |
UIO_REGMAP 🔗
UIO_REGS 🔗
UIO
Offset 0x0000: IP Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Set this port's IP address
Offset 0x0004: UDP Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Set the UDP port for CHDR_traffic
Offset 0x0010: BRIDGE_MAC_LSB Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this MAC_ID
Offset 0x0014: BRIDGE_MAC_MSB Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this MAC_ID
Offset 0x0018: BRIDGE_IP Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this IP Address
Offset 0x001C: BRIDGE_UDP Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic
Offset 0x0020: BRIDGE_ENABLE Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Bit 0 Controls the following logic
always_comb begin : bridge_mux
my_mac = bridge_en ? bridge_mac_reg : mac_reg;
my_ip = bridge_en ? bridge_ip_reg : ip_reg;
my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
end
Offset 0x0030: CHDR_DROPPED Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Count the number of Packets dropped that were addressed to the CHDR section.
Offset 0x0034: CPU_DROPPED Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Count the number of Packets dropped that were addressed to us, but not to the CHDR section.
Offset 0x0038: PAUSE Register (R|W) 🔗
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Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
| Bits | Name |
| 31..16 |
If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause. Pause clear must be less than pause set or terrible things will happen. The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only used with 100Gb ethernet |
| 15..0 |
If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only used with 100Gb ethernet |
VERSIONING_REGS_REGMAP 🔗
VERSIONING_CONSTANTS 🔗
CPLD_IFC_VERSION Enumeration 🔗
CPLD interface module.For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 2 | 0x00000002 | |
| 2 | 0x00000002 | |
| 553719817 | 0x21011809 | |
This enumerated type is defined in HDL source file cpld_interface_regs.v.
DB_GPIO_IFC_VERSION Enumeration 🔗
Daughterboard GPIO interface.For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 621150997 | 0x25060315 | |
This enumerated type is defined in HDL source file db_gpio_interface.sv.
FPGA_VERSION Enumeration 🔗
FPGA version.For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 11 | 0x0000000B | |
| 11 | 0x0000000B | |
| 637675285 | 0x26022715 | |
This enumerated type is defined in HDL source file x4xx.sv.
RF_CORE_1000M_VERSION Enumeration 🔗
1000 MHz RF core.For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 2 | 0x00000002 | |
| 2 | 0x00000002 | |
| 621937424 | 0x25120310 | |
This enumerated type is defined in HDL source file rf_core_1000m.sv.
RF_CORE_FULL_VERSION Enumeration 🔗
Full BW RF core.For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 604506389 | 0x24080915 | |
This enumerated type is defined in HDL source file rf_core_full.sv.
VERSIONING_REGS 🔗
COMPONENTS_INDEXES Enumeration 🔗
This enum contains indexes for all the components in the X410 (both common and app-specific) which version information is desired to be available for compatibility tracking purposes.| Description | Index range | Max # of components |
|---|---|---|
| Common components | 0 to 23 | 24 |
| UHD-specific components | 24 to 43 | 20 |
| LV-specific components | 44 to 63 | 20 |
| Value | Name |
| 0 | |
| 1 | |
| 2 | |
| 3 | |
| 4 | |
| 5 |
This enumerated type is defined in HDL source file x4xx_versioning_regs.v.
Offset 0x0000: CURRENT_VERSION (63:0) Register Array (R) 🔗
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Intial Values
| default | => | 0x00000000 |
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType VERSION_TYPE which is
defined in HDL source file x4xx_versioning_regs.v.
This register contains the current component's version implemented in HDL. The current version shall be used to detect a component being too old for the driver/software:
SW oldest compatible version > Component's current version --> Component is too old.
| Bits | Name |
| 31..23 |
Major number (max = 511): an increase reflects a breaking change. |
| 22..12 |
Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of. |
| 11..0 |
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
but that should not impact the component's behavior |
Offset 0x0004: OLDEST_COMPATIBLE_VERSION (63:0) Register Array (R) 🔗
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Intial Values
| default | => | 0x00000000 |
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType VERSION_TYPE which is
defined in HDL source file x4xx_versioning_regs.v.
This register contains the oldest compatible component's version, that is the oldest component's implementation that is compatible with the current implementation.
The oldest compatible version shall be used to detect a component being too new for the driver/software:
SW current version < Component's oldest compatible version --> Component is too new.
| Bits | Name |
| 31..23 |
Major number (max = 511): an increase reflects a breaking change. |
| 22..12 |
Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of. |
| 11..0 |
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
but that should not impact the component's behavior |
Offset 0x0008: VERSION_LAST_MODIFIED (63:0) Register Array (R) 🔗
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Initial Value not specified
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType TIMESTAMP_TYPE which is
defined in HDL source file x4xx_versioning_regs.v.
This register provides the time stamp for the last modification to the component's versions (current & oldest compatible). The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
| Bits | Name |
| 31..24 |
This is the year number after 2000 (e.g. 2019 = 0x19). |
| 23..16 | |
| 15..8 | |
| 7..0 |
Offset 0x000C: RESERVED (63:0) Register Array (R) 🔗
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Initial Value not specified
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType RESERVED_TYPE which is
defined in HDL source file x4xx_versioning_regs.v.
X4XX_DB_SPI_REGMAP 🔗
This is a dummy regmap to have a common name for the regmap behind the SPI interface of the DB CPLD.DB_WINDOW 🔗
Offset 0x0000: SPI_WINDOW Window (R|W) 🔗
Target regmap = HBX_SPI_REGMAP
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This window is defined in HDL source file hbx_top_cpld.sv.
XGE_MAC_REGMAP 🔗
OPENCORE_XGE_REGISTERS 🔗
10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf