Table of Contents
The UHD will automatically select the USRP embedded FPGA image from the installed images package. The FPGA image selection can be overridden with the "fpga" device address parameter.
Example device address string representations to specify non-standard FPGA image:
fpga=usrp_e100_custom.bin
The master clock rate of the USRP embedded feeds both the FPGA DSP and the codec chip. Hundreds of rates between 32MHz and 64MHz are available. A few notable rates are:
To use the 61.44MHz clock rate, the USRP embedded will require two jumpers to be moved.
Note: See instructions below to communicate the desired clock rate into the UHD.
To use other clock rates, the jumpers will need to be in the default position.
To communicate the desired clock rate into the UHD, specify the a special device address argument, where the key is "master_clock_rate" and the value is a rate in Hz. Example:
uhd_usrp_probe --args="master_clock_rate=52e6"
It is possible to set a clock rate such that the UHD can no longer communicate with the FPGA. When this occurs, it is necessary to use the usrp-e-utility to recover the clock generator. The recovery utility works by loading a special pass-through FPGA image so the computer can talk directly to the clock generator over a SPI interface.
Run the following commands to restore the clock generator to a usable state:
cd <install-path>/share/uhd/usrp_e_utilities ./usrp-e-utility --fpga=../images/usrp_e100_pt_fpga.bin --reclk
The E1xx has a 10MHz TCXO which can be used to discipline the flexible clocking by selecting REF_INT for the clock_config_t.
Alternately, an external 10MHz reference clock can be supplied by soldering a connector.
An exteral PPS signal for timestamp synchronization can be supplied by soldering a connector.
Test the PPS input with the following app:
cd <install-path>/share/uhd/examples ./test_pps_input --args=<args>