Comparative features list - B200/B210

Hardware Capabilities:
- Integrated RF frontend (70 MHz - 6 GHz)
- External PPS reference input
- External 10 MHz reference input
- Configurable clock rate
- Variable analog bandwidth (200 kHz - 56 MHz)
- Internal GPSDO option (see Internal GPSDO Application Notes (USRP-B2x0 Models) for details)
- B210 Only:
  - MICTOR Debug Connector
  - JTAG Connector
- Revision 6 with GPIO header
FPGA Capabilities:
- Timed commands in FPGA
- Timed sampling in FPGA

Specify a Non-standard Image

UHD software will automatically select the USRP B2X0 images from the installed images package. The image selection can be overridden with the fpga and fw device address parameters.

Example device address string representations to specify non-standard images:

fpga=usrp_b200_fpga.bin

-- OR --

fw=usrp_b200_fw.hex

Changing the Master Clock Rate

The master clock rate feeds the RF frontends and the DSP chains. Users may select non-default clock rates to acheive integer decimations or interpolations in the DSP chains. The default master clock rate defaults to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz.

The user can set the master clock rate through the usrp API call uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the device arguments, which many applications take: :

uhd_usrp_probe --args="master_clock_rate=52e6"

RF Frontend Notes

The B200 features an integrated RF frontend.

Frontend tuning

The RF frontend has individually tunable receive and transmit chains. On the B200, there is one transmit and one receive RF frontend. On the B210, both transmit and receive can be used in a MIMO configuration. For the MIMO case, both receive frontends share the RX LO, and both transmit frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz.

Frontend gain

All frontends have individual analog gain controls. The receive frontends have 73 dB of available gain; and the transmit frontends have 89.5 dB of available gain. Gain settings are application specific, but it is recommended that users consider using at least half of the available gain to get reasonable dynamic range.

Frontend bandwidth

The analog frontend has a seamlessly adjustable bandwidth of 200 kHz to 56 MHz.

Generally, when requesting any possible master clock rate, UHD will automatically configure the analog filters to avoid any aliasing (RX) or out-of-band emissions whilst letting through the cleanest possible signal.

If you, however, happen to have a very strong interferer within half the master clock rate of your RX LO frequency, you might want to reduce this analog bandwidth. You can do so by calling uhd::usrp::multi_usrp::set_rx_bandwidth(bw).

The property to control the analog RX bandwidth is bandwidth/value.

UHD will not allow you to set bandwidths larger than your current master clock rate.

Reference

Indicators

Below is a table of the LED indicators and their meanings:

Component ID	Description	Details
LED600	Power Indicator	off = no power applied red = power applied (external or USB)
LED800	Channel 2 RX2 Activity	off = no power applied green = receiving
LED801	Channel 2 TX/RX Activity	off = no activity green = receiving red = transmitting orange = switching between transmitting and receiving
LED802	Channel 1 TX/RX Activity	off = no activity green = receiving red = transmitting orange = switching between transmitting and receiving
LED803	Channel 1 RX2 Activity	off = no power applied green = receiving
LED100	GPS lock indicator	off = no lock green = lock

TX LED indicators are on when transimitting data and off when no samples are available to transmit. RX LED indicators are on when sending samples to the host and off when unable to do so. This means that TX/RX activity LED indicators will blink off in a temporary transmit underflow or receive overflow condition, indicating that the host is not sending or receiving samples fast enough. The host will be notified of the condition and output a "U" or "O" as well.

Connections

Below is a table showing the external connections and respective power information:

Component ID	Description	Details
J601	External Power	6 V 3 A
J701	USB Connector	USB 3.0
J104	External PPS Input	1.8 V - 5 V
J101	GPS Antenna	GPSDO will supply nominal voltage to antenna.
J100	External 10 MHz Input	+15 dBm max</td
J800	RF B: TX/RX	TX power +20dBm max RX power -15dBm max
J802	RF B: RX2	RX power -15dBm max
J803	RF A: RX2	RX power -15dBm max
J801	RF A: TX/RX	TX power +20dBm max RX power -15dBm max

On-Board Connectors and Switches

Below is a table showing the on-board connectors and switches:

Component ID	Description	Details
J502¹	Mictor Connector	Interface to FPGA for I/O and inspection.
J503¹	JTAG Header	Interface to FPGA for programming and debugging.
J504²	GPIO Header	Header running to the FPGA for GPIO purposes.
S700	FX3 Hard Reset Switch	Resets the USB controller / System reset
U100	GPSDO socket	Interface to GPS disciplined reference oscillator

¹ Only on the B210

² Only since rev. 6 (green board)

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