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USRP Hardware Driver and USRP Manual Version: 4.1.0.1
UHD and USRP Manual
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USRP Hardware Driver and USRP Manual Version: 4.1.0.1
UHD and USRP Manual
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The USRP FPGA build system requires a UNIX-like environment with the following dependencies
The following USRPs work with the free WebPack versions:
Download and install Xilinx Vivado or Xilinx ISE based on the target USRP.
/opt/Xilinx/ for Linux and C:\Xilinx in Windows.If you prefer to use ModelSim, download and install Mentor ModelSim using the link above.
/opt/mentor/modelsim for Linux and C:\mentor\modelsim in WindowsYou can install all the dependencies through the package manager:
sudo apt-get install python bash build-essential doxygen
Your actual command may differ.
You can install all the dependencies through the package manager:
sudo yum -y install python bash make doxygen
Your actual command may differ.
NOTE: Windows is only supported with Vivado. The build system does not support Xilinx ISE in Windows.
Download the latest version on Cygwin (64-bit is preferred on a 64-bit OS) and install it using these instructions. The following additional packages are also required and can be selected in the GUI installer
python3 patch patchutils bash make gcc-core doxygen
<repo>/fpga/usrp3/top/{project} where {project} is:x300: For USRP X300 and USRP X310e31x: For USRP E310e320: For USRP E320n3xx: For USRP N300/N310/N320x400: For USRP X410source setupenv.sh (If Vivado is installed in the default path /opt/Xilinx/Vivado) ORsource setupenv.sh --vivado-path=<VIVADO_PATH> (where VIVADO_PATH is a non-default installation path)make <target> where the target is specific to each product. To get a list of supported targets run make help.<repo>/fpga/usrp3/top/{project}/build directory. Run make help for more information.The build environment also defines many ease-of-use utilities. Please use the Vivado Utility Reference page for a list and usage information
source <install_dir>/Xilinx/14.7/ISE_DS/settings64.sh (64-bit platform)source <install_dir>/Xilinx/14.7/ISE_DS/settings32.sh (32-bit platform)<repo>/fpga/usrp3/top/{project} where {project} is:make <target> where the target is specific to each product. To get a list of supported targets run make help.<repo>/fpga/usrp3/top/{project}/build directory. Run make help for more information.build/usrp_<product>_fpga.bit : Configuration bitstream with headerbuild/usrp_<product>_fpga.bin : Configuration bitstream without headerbuild/usrp_<product>_fpga.syr : Xilinx system reportbuild/usrp_<product>_fpga.twr : Xilinx timing reportbuild/usrp_<product>_fpga_<image_type>.bit : Configuration bitstream with headerbuild/usrp_<product>_fpga_<image_type>.bin : Configuration bitstream without headerbuild/usrp_<product>_fpga_<image_type>.lvbitx : Configuration bitstream for PCIe (NI-RIO)build/usrp_<product>_fpga_<image_type>.rpt : System, utilization and timing summary reportbuild/usrp_<product>_fpga.bit : Configuration bitstream with headerbuild/usrp_<product>_fpga.dts : Device tree overlaybuild/usrp_<product>_fpga.rpt : System, utilization and timing summary reportbuild/usrp_<product>_fpga.bit : Configuration bitstream with headerbuild/usrp_<product>_fpga.dts : Device tree overlaybuild/usrp_<product>_fpga.rpt : System, utilization and timing summary reportThe targets depend on the actual hardware the FPGA image is being deployed to. Unlike the X300 Series, the daughterboards are an integral part of the module and not meant to be removed. Therefore, the target is specific to the combination of motherboard and daughterboards.
For the N320 targets see also the N320 manual page on the UHD manual.
build/usrp_<product>_fpga.bit : Configuration bitstream with headerbuild/usrp_<product>_fpga.dts : Device tree overlaybuild/usrp_<product>_fpga.rpt : System, utilization and timing summary reportUnlike the USRP X310, the target types do not only describe the connector configuration, but also the available master clock rates. For example, the FPGA target type X4_200 is configured for a 200 MHz analog bandwidth, and can support a 245.76 MHz or 250 MHz master clock rate.
A more detailed description of the targets can be found at FPGA Image Flavors. The following targets are available through the Makefile:
X1_100X4_{100, 200}XG_{100, 200}X4_{100, 200}The following bitstreams can be built, but are considered experimental:
X4C_{100, 200}C1_400CG_{100, 400}build/usrp_<product>_fpga.bit : Configuration bitstream with headerbuild/usrp_<product>_fpga.dts : Device tree overlaybuild/usrp_<product>_fpga.rpt : System, utilization and timing summary reportIt is possible to make a target and specify additional options in the form VAR=VALUE in the command. For example:
$ make X310 GUI=1
The options available are described in the following subsections.
GUI=1 : Run the Vivado build in GUI mode instead of batch mode. After the build is complete, Vivado provides an option to save the fully configured project for customizationCHECK=1 : Run elaboration only to check HDL syntaxSYNTH=1 : Run synthesis onlyTOP=<module> : Specify an alternate top-level module for syntax checkingPROJECT_ONLY=1 : Only create a Xilinx project for the specified target(s). Useful for use with the ISE GUI.EXPORT_ONLY=1 : Export build targets from a GUI build to the build directory. Requires the project in build-*_* to be built. 
1.9.3