USRP Hardware Driver and USRP Manual  Version: 003.010.001.001-11-g16ccfe21
UHD and USRP Manual
USRP B2x0 Series

Comparative features list - B200/B210/B200mini

  • Hardware Capabilities:
    • Integrated RF frontend (70 MHz - 6 GHz)
    • External PPS reference input
    • External 10 MHz reference input
    • Configurable clock rate
    • Variable analog bandwidth (200 kHz - 56 MHz)
    • GPIO header
    • [B200/B210] Internal GPSDO option (see Internal GPSDO Application Notes (USRP-B2x0 Models) for details)
    • [B210/B200mini] JTAG Connector
    • [B210] MICTOR Debug Connector
  • FPGA Capabilities:
    • Timed commands in FPGA
    • Timed sampling in FPGA

Power

In most cases, USB 3.0 bus power will be sufficient to power the device. If using USB 2.0 or a GPSDO, an external power supply or a cable designed to pull power from 2 USB ports (USB 3.0 dual A to micro-B or B) must be used.

Specifying a Non-standard Image

UHD software will automatically select the USRP B2X0 images from the installed images package. The image selection can be overridden with the fpga and fw device address parameters.

Example device address string representations to specify non-standard images:

fpga=usrp_b200_fpga.bin

-- OR --

fw=usrp_b200_fw.hex

Changing the Master Clock Rate

The master clock rate feeds the RF frontends and the DSP chains. Users may select non-default clock rates to achieve integer decimation rates or interpolations in the DSP chains. The clock rate can be set to any value between 5 MHz and 61.44 MHz (or 30.72 MHz for dual-channel mode). Note that rates above 56 MHz are possible, but not recommended.

The user can set the master clock rate through the usrp API call uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the device arguments, which many applications take:

uhd_usrp_probe --args="master_clock_rate=52e6"

The property to control the master clock rate is a double value, called tick_rate.

Automatic Clock Rate Setting

The default clock rate setting is to automatically set a clock rate depending on the requested sampling rate. The automatic clock rate selection is disabled when either master_clock_rate is given in the device initialization arguments, or when uhd::usrp::multi_usrp::set_master_clock_rate() is called.

Note that the master clock rate must be an integer multiple of the sampling rate. If a master clock rate is chosen for which this condition does not hold, a warning will be displayed and a different sampling rate is used internally.

Nevertheless, there are multiple valid values for the master clock rate for most sampling rates. The auto clock rate selection attempts to use the largest possible clock rate as to enable as many half-band filters as possible. Expert users might have cases where a more fine-grained control over the resampling stages is required, in which case manually selecting a master clock rate might be more suitable than the automatic rate.

The property to dis- or enable the auto tick rate is a boolean value, auto_tick_rate.

RF Frontend Notes

The B200 features an integrated RF frontend.

Frontend tuning

The RF frontend has individually tunable receive and transmit chains. On the B200 and B200 mini, there is one transmit and one receive RF frontend. On the B210, both transmit and receive can be used in a MIMO configuration. For the MIMO case, both receive frontends share the RX LO, and both transmit frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz.

Frontend gain

All frontends have individual analog gain controls. The receive frontends have 73 dB of available gain; and the transmit frontends have 89.5 dB of available gain. Gain settings are application specific, but it is recommended that users consider using at least half of the available gain to get reasonable dynamic range.

Frontend bandwidth

The analog frontend has a seamlessly adjustable bandwidth of 200 kHz to 56 MHz.

Generally, when requesting any possible master clock rate, UHD will automatically configure the analog filters to avoid any aliasing (RX) or out-of-band emissions whilst letting through the cleanest possible signal.

If you, however, happen to have a very strong interferer within half the master clock rate of your RX LO frequency, you might want to reduce this analog bandwidth. You can do so by calling uhd::usrp::multi_usrp::set_rx_bandwidth(bw).

The property to control the analog RX bandwidth is bandwidth/value.

UHD will not allow you to set bandwidths larger than your current master clock rate.

Reference

Indicators

Below is a table of the B200/B210 LED indicators and their meanings:

Component IDDescriptionDetails
LED600 Power Indicator off = no power applied
red = external power applied
blue(red prior to rev 6) = USB power applied
LED800 Channel 2 RX2 Activity off = no power applied
green = receiving
LED801 Channel 2 TX/RX Activity off = no activity
green = receiving
red = transmitting
orange = switching between transmitting and receiving
LED802 Channel 1 TX/RX Activity off = no activity green = receiving
red = transmitting
orange = switching between transmitting and receiving
LED803 Channel 1 RX2 Activity off = no power applied
green = receiving
LED100 GPS lock indicator off = no lock
green = lock

Below is a table of the B200mini LED indicators and their meanings:

Component IDDescriptionDetails
PWR LED Power Indicator off = no power applied
on = power applied (external or USB)
TRX LED TX/RX Activity off = no activity
green = receiving
red = transmitting
orange = switching between transmitting and receiving
RX2 LED RX2 Activity off = no activity
green = receiving
S0 LED Reference Lock off = no activity green = locked
S1 LED Reference Present off = reference level low or not present
green = reference level high

TX LED indicators are on when transmitting data and off when no samples are available to transmit. RX LED indicators are on when sending samples to the host and off when unable to do so. This means that TX/RX activity LED indicators will blink off in a temporary transmit underflow or receive overflow condition, indicating that the host is not sending or receiving samples fast enough. The host will be notified of the condition and output a "U" or "O" as well.

Connections

Below is a table showing the B200/B210 external connections and respective power information:

Component ID Description Details
J601 External Power 6 V
3 A
J701 USB Connector USB 3.0
J104 External PPS Input 1.8 V - 5 V
J101 GPS Antenna GPSDO will supply nominal voltage to antenna.
J100 External 10 MHz Input +15 dBm max
J800 RF B: TX/RX TX power +20dBm max
RX power -15dBm max
J802 RF B: RX2 RX power -15dBm max
J803 RF A: RX2 RX power -15dBm max
J801 RF A: TX/RX TX power +20dBm max
RX power -15dBm max

Below is a table showing the B200mini external connections and respective power information:

Component ID Description Details
USB3 USB Connector USB 3.0
J1 TRX TX power +20dBm max
RX power -15dBm max
J2 RX2 RX power -15dBm max
J3 External 10MHz/PPS Reference +15 dBm max

On-Board Connectors and Switches

Below is a table showing the B200/B210 on-board connectors and switches:

Component ID Description Details
J5021 Mictor Connector Interface to FPGA for I/O and inspection.
J5031 JTAG Header Interface to FPGA for programming and debugging.
J5042 GPIO Header Header connected to the FPGA for GPIO purposes.
S700 FX3 Hard Reset Switch Resets the USB controller / System reset
U100 GPSDO socket Interface to GPS disciplined reference oscillator

1 Only on the B210

2 Only since rev. 6 (green board). GPIO pinout is 1=GPIO_0, 2=GPIO_1, 3=GPIO_2, 4=GPIO_3, 5=GPIO_4, 6=GPIO_5, 7=GPIO_6, 8=GPIO_7, 9=GND, 10=GND

Below is a table showing the B200mini on-board connectors and switches:

Component ID Description Details
J5 JTAG Header Interface to FPGA for programming and debugging.
J61 GPIO Header Header connected to the FPGA for GPIO purposes.
SW1 FX3 Hard Reset Switch Resets the USB controller / System reset

1 GPIO pinout is 1=3.3V, 2=GPIO_0, 3=GPIO_1, 4=GPIO_2, 5=GPIO_3, 6=GND, 7=3.3V, 8=GPIO_4, 9=GPIO_5, 10=GPIO_6, 11=GPIO_7, 12=GND